Low-cost emerging market SoC/phone discussion

[Rys]

Since I have the data in front of me (across 3 separate Exynos 4+4 A7+A15 big.LITTLE configurations), the ratio of area between A7s and A15s varies a lot. 1/6th was true for just one of those Exynos chips.

EDIT: I said 4 chips before, it's really just 3. One of them is A57+A53 (5433).

 

[Erinyes]

Samsung's material shows a A7 core taking 1/6 the die area and roughly 1/6 the power usage, at a significantly lower top frequency than the A15.
When paired with a 1/4 of the L2 cache of the A15, the die area scale is then 1/5.

http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13

Assuming the same cache proportions; a 2xA15+2xA17 configuration would use 11.4mm2 for cores and cache, while a 4xA7+4xA7 configuration would use 7.6mm2.

Well the link you've provided actually shows that the A7 cores take up exactly 1/5 of the die area of the A15 cores (3.8 mm2 vs 19 mm2). And the A7 cores have only 512 KB L2 cache. It is 1 MB in the two most popular quad core A7 SoCs, i.e. MT6589 and MSM8x26. So in reality the ratio should be a bit lower even, probably closer to 1/4.

However, as Rys says, this will vary based on the implementation.

Since I have the data in front of me (across 3 separate Exynos 4+4 A7+A15 big.LITTLE configurations), the ratio of area between A7s and A15s varies a lot. 1/6th was true for just one of those Exynos chips.

Thanks for the info Rys. Is the area of the A7s highly dependent on the amount of L2 cache or are there other factors? (I understand that A7 was designed to be easily synthesizable and has very little custom logic compared to say A8)

Also..the link posted by kalelovil shows that the A15s consume about 6 times the power of the A7s. I am assuming this is at their max clocks which is listed as 1.8 ghz for the A15s and 1.2 ghz for the A7s. Is this correct or is the power actually 6x at the same clocks?

EDIT: I said 4 chips before, it's really just 3. One of them is A57+A53 (5433).

Could you possibly divulge any further details on the die area and power differences between A57 and A53? Comparison to A15 and A7 also would be highly appreciated

 

[kalelovil]

Well the link you've provided actually shows that the A7 cores take up exactly 1/5 of the die area of the A15 cores (3.8 mm2 vs 19 mm2). And the A7 cores have only 512 KB L2 cache. It is 1 MB in the two most popular quad core A7 SoCs, i.e. MT6589 and MSM8x26. So in reality the ratio should be a bit lower even, probably closer to 1/4.

The 3.8mm2 and 19mm2 figures presumably include the L2 cache, since the A7 cores should only be 0.5mm2 each, but indeed if you give the A7 cores more cache the total area advantage over the A15 will diminish.

 

[Rys]

The 3.8mm2 and 19mm2 figures presumably include the L2 cache, since the A7 cores should only be 0.5mm2 each, but indeed if you give the A7 cores more cache the total area advantage over the A15 will diminish.

3.8mm2 and 19mm2 aren't exactly right on 5410. The A7 cores on that chip are bigger than 0.5mm2 without counting L2.

 

[Rys]

Thanks for the info Rys. Is the area of the A7s highly dependent on the amount of L2 cache or are there other factors? (I understand that A7 was designed to be easily synthesizable and has very little custom logic compared to say A8)

A7 (and A15) area is highly variable even across all the chips I've seen, and that's without factoring in L2. In every implementation I've seen, the A7 cluster has each core sharing synthesis.

Could you possibly divulge any further details on the die area and power differences between A57 and A53? Comparison to A15 and A7 also would be highly appreciated

No comment on power. I've only ever seen one implementation of A57 and A53, so I don't have much data. However, A57 is ~20% larger than A15 and A53 is ~80% larger than A7, same process, same vendor. There's much less of a gap in area between A57 and A53 (at least for my one sample point) than A15 and A7. A53's pretty big (if you can call a fully-fledged high performance modern core that's less than 1mm2 fully laid out, "big").

 

[liolio]

Congratulation Ailuros

 

[Erinyes]

A7 (and A15) area is highly variable even across all the chips I've seen, and that's without factoring in L2. In every implementation I've seen, the A7 cluster has each core sharing synthesis.

Interesting. Is this due to the usual tradeoffs between area and power? Or is there any other factor which influences this?

No comment on power. I've only ever seen one implementation of A57 and A53, so I don't have much data. However, A57 is ~20% larger than A15 and A53 is ~80% larger than A7, same process, same vendor. There's much less of a gap in area between A57 and A53 (at least for my one sample point) than A15 and A7. A53's pretty big (if you can call a fully-fledged high performance modern core that's less than 1mm2 fully laid out, "big").

Thanks! Much appreciate the info :smile: Yes..seems like the gap has narrowed significantly between A57 and A53. ARMv8 support on A53 seems to have been expensive in terms of die area. If we go by ARMs performance numbers, both A57 and A53 increase performance by ~40% over A15 and A7 respectively, at the same node. So A57 got there with a 20% increase in size, but A53 needed 80%. (Source - Anandtech)

I am also curious on the L2 cache size, presumably it would be 2 MB for the quad A57 cluster and 1 MB for the A53 cluster?

 

[Rys]

Interesting. Is this due to the usual tradeoffs between area and power? Or is there any other factor which influences this?

If there's one thing Samsung LSI aren't scared of, it's using area if they need it. While they're as sensitive to cost as everyone else, on these high-end SoCs they'll definitely spend area to make it easier to manage power. Every Exynos I've seen is like that.

A15 isn't a low-power IP by any means, so you can understand why they'd have the motivation to manage power in the first place.

I am also curious on the L2 cache size, presumably it would be 2 MB for the quad A57 cluster and 1 MB for the A53 cluster?

Good question. I don't think that's the ratio on Exynos 5433, but I haven't looked at the A53 array too closely yet (and for the first time in a long time, I have a die shot before I have a device). Nebu might have more information on L2 sizes from his work looking at kernel sources.

 

[Nebuchadnezzar]

Good question. I don't think that's the ratio on Exynos 5433, but I haven't looked at the A53 array too closely yet (and for the first time in a long time, I have a die shot before I have a device). Nebu might have more information on L2 sizes from his work looking at kernel sources.

Cache sizes are completely transparent to the OS even at the kernel level. Rarely do they expose this through debug stuff from dumping the whole caches into a dedicated RAM space (Qualcomm), and never in SLSI's case.

I could figure out the sizes by using our memory latency test but I still don't have a 5433 device... soo...

 

[Rys]

Cache sizes are completely transparent to the OS even at the kernel level. Rarely do they expose this through debug stuff from dumping the whole caches into a dedicated RAM space (Qualcomm), and never in SLSI's case.

I could figure out the sizes by using our memory latency test but I still don't have a 5433 device... soo...

Interesting, I thought that kind of stuff was exposed in the kernel. I'll figure it out at some point from the die.

 

[Ailuros]

Thank you guys for the wishes . I need to chew on the A5x data provided hopefully tomorrow when we can bring the 7 pounds of newly obtained happiness home.

 

[tangey]

nice one

 

[Erinyes]

If there's one thing Samsung LSI aren't scared of, it's using area if they need it. While they're as sensitive to cost as everyone else, on these high-end SoCs they'll definitely spend area to make it easier to manage power. Every Exynos I've seen is like that.

A15 isn't a low-power IP by any means, so you can understand why they'd have the motivation to manage power in the first place.

Yes..for high end designs it would be much more prudent to use area if it can help power. IIRC they were doing this even with their Cortex A9 SoCs earlier (Cortex A8 too though I'm hazy on whether that was them or Intrinsity)

PS: I forgot to mention one thing earlier in our discussion on die sizes. Quad Cortex A15s with 2 MB L2 were 19mm2. In comparison a dual core Cyclone with 1 MB L2 is 17 mm2. It really puts things in perspective how large Apple's cores are.

Good question. I don't think that's the ratio on Exynos 5433, but I haven't looked at the A53 array too closely yet (and for the first time in a long time, I have a die shot before I have a device). Nebu might have more information on L2 sizes from his work looking at kernel sources.

I'm suppose you're more interested in the T760 GPU on that chip But if you have die shots of both 5430 and 5433, a quick analysis should suffice to determine the cache size no? Either way..looking forward to your results whenever you get the time :smile:

 

[Rys]

2MB on the A15s, 512KB on the A7s, for 5430. Haven't had time to look at 5433 properly. The A53 cluster on that chip neighbours some busy, SRAM-heavy logic that makes it harder to delineate the A53's L2 cells. From a top-level eyeball it's probably the same though.

 

[Ailuros]

Ok let's take it once more from the top:

Assuming an A7 costs you 1/4th in die area compared to an A15 and freely inventend figures for 2mm2 for each A15 and 0.5mm2 for each A7:

* 4xA15 + 4xA7 = 10 mm2
* 8xA7 = 4 mm2

First case delivers far more overall performance but also at the cost of significantly more die area and power consumption. If you're Mediatek, Rockchip or whoever else that wants to sell a lot of relatively small SoCs at very low prices, you'd obviously would avoid an as big core as A15 as much as possible.

The only other spot where MTK so far used A15 cores was in the MT8135 being a tablet SoC with 2*A15 + 2*A7. Their current "high end" smartphone SoC the MT6595 has a 4+4 config but the "big" cores are A17 cores.

Their recent "high end smartphone" roadmap went like this:

1. MT6589 = 4*A7
2. MT6592 = 8*A7
3. MT6595 = 4*A17+4*A7
4. MT6795 = (I assume) 8*A53?

Even after Rys' clarification I doubt they'll go for a 4*A57+4*A53 config; not impossible but they'll still save die area (less of course than before) with a theoretical 8*A53 config.

 

[Deleted member 13524]

I doubt they would do the MT6795 with 8*A53 because it would probably get lower scores than MT6595.
Seeing how the chinese rely so much on antutu scores, it would be really bad for them to present the new chip working slower than the old.

 

[Ailuros]

I doubt they would do the MT6795 with 8*A53 because it would probably get lower scores than MT6595.
Seeing how the chinese rely so much on antutu scores, it would be really bad for them to present the new chip working slower than the old.

Do we know how a A53 fairs in real time compared to A17/A7 cores?

 

[Laurent06]

Do we know how a A53 fairs in real time compared to A17/A7 cores?

Cortex-A17 vs Cortex-A53 on Geekbench
The A17 is in another league, it should be compared against A15.

 

[Deleted member 13524]

Here's what seems to be a great quality smartphone with a MT6595:

http://www.pandawill.com/lenovo-vib...hd-screen-2gb-16gb-glonass-golden-p93566.html

 

[Ailuros]

Cortex-A17 vs Cortex-A53 on Geekbench
The A17 is in another league, it should be compared against A15.

I realize that. Thanks for the comparison, which means that Tottentranz obviously has a point above.