Gubbi said:
Bandwidth is easy, just throw pins at the problem and scale frequency. Latency is limited by a nasty physical constant, c.
Historically, the main reason for using embedded DRAM has always been bandwidth. Before R300 many people said a 256-bit memory bus was crazy, (frankly, it still does feel crazy to me) and I'm not quite sure if the world is ready for 2000-pin chips... and scaling memory frequency isn't particularly easy (memory frequencies are scaling significantly slower than core clock frequencies both in CPU's and VPU's).
I'm not sure c really comes into one more than the other.