Larrabee Die-Shot - Analyze this

Discussion in 'Architecture and Products' started by CarstenS, May 12, 2009.

  1. LordEC911

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    Obviously much more than $200... (yes that is a shot at G200)
    I would guess it would be priced competitively depending upon performance, at least for the gaming market.

    I really don't see Intel being able to hit the ground running with gamers, especially trying to keep up with AMD/ATi and Nvidia.

    I have to wonder if they will have special(drivers/instructions?) Larrabees for the professional market and sell them for $1000-$3000 a pop?
     
  2. Rufus

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    The 4 blue bits are almost certainly the memory controller connections - 4 of them right next to the 4 groups of I/O pads. It is a bit odd that the 4 memory controllers + pads aren't aligned at the same location, meaning the timing on the 4 interconnects are completely unique (and possibly even have different latency, depending on distance, clock frequency, and retiming registers stages needed).

    The I/O's on the right I'm guessing are display and PCIe. The odd-shaped unique blocks on the right are probably the drivers for those interfaces, and whatever system-level stuff is needed (if there is any).

    I have absolutely no idea what the blob on the top-left is. There aren't any I/O pads next to it, and it's in an awkward position to have anything to do with the network.

    The main thing I'm wondering about is what the interconnect network is. All of the papers and slides shown so far have specifically said it will be using a ring-bus, which just doesn't work elegantly at all with 3 rows. The arrangement of 3 tex units on the top/bottom row and 2 units in the middle row imply that the middle somehow evenly connects to both the top and the bottom. However evenly connecting to both means having 2 rings going through the middle cores and only 1 ring going through the top/bottom ones, which means wasting lots of routing resources on the top/bottom ones (since I assume all the cores are identical and stamped out). My guess is there are somehow 2 rings, and the 2 connect to a crossbar somewhere on the right (xbar connects the 2 rings to each other and to PCIe and display).

    Anyone have any guesses as to where the rings are, and which cores they connect to?
     
  3. PeterT

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    I have also thought about this, 2 rings of 16 cores and 4 TUs each would fit with the Larrabee whitepaper (which says that more than 16 cores use multiple rings), but it's hard to see how it would work with the layout in the die shot. You could have one ring on the left and one on the right, or maybe have one on top and one on the bottom with units in the center connecting either way, but neither option seems to make much topological sense.
     
  4. 3dilettante

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    Debugging hardware, possibly.

    There's no physical reason for a ring bus to be an actual ring.
    The most even distribution of texture units, assuming two 16 core rings, would appear to me to be to divide the chip into two (rough) triangles, with some kind of zig zag across the necessary cores. I'm still thinking on that.
     
    #44 3dilettante, May 13, 2009
    Last edited by a moderator: May 13, 2009
  5. Jawed

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    Yep, it'd be pretty funny if a Hilbert or Morton curve was implemented to make the rings :razz: A sort of fixed-function rasterisation joke lying in the hardware :lol:

    Jawed
     
  6. PhilTaylor

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  7. CarstenS

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    Nice - in the opening of the Intel Visual Computing Institute at the Saarland University, one of the speakers said something about "... or larrabee later this year." ;)
     
  8. Scali

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    Well, Intel has been saying for a long time that they would be demonstrating working hardware in the second half of '09. So that doesn't surprise me.
    In fact, it seems logical that they have some working prototypes by the end of this year if they want to release it early 2010.

    Can't wait to see their stuff in action though. I want to know how good their solution is in practice.
     
  9. hcpizzi

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    I read somewhere, probably in one of the GDC conference slides, that the ring bus wasn't really a ring bus, but that it was easier to think about it as if it were.
     
  10. keritto

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    Did you conclude that simply byextracting the above numbers ... RV770 is55nm and
    gt200 was 65nm at the start so it's fairly 1.5x and 2x bigger litograph printout than this probably 45nm prototype :lol:

    I agree with you that those belowe we had 384-bits memory interface but i believe it's only half of it and the other half you all forget so it's probably 512-bit GDDR5 and 256-bit DDR3 to fulfill all kind of marketing necessities. If it's true that 20x30=600mm chip size @45nm with the real life 32nm product with ~300mm2 somehow i dont thin there'll be more than maybe 40% fully functional 32core chip and for some poor 16core OCed to some 2GHz Quad-DDR3 would be more than sufficient to place it on budget market of overgrown enthusiasts for let's say 400USD ... Well they need geeks that'll help in developing some crap software to make actual product launch. Not like amd with 1.5year paper launch of x2 in reality with niche market

    Here are some of my insight (btw. PeterT where did you found that bigger resolution picture)
    [​IMG]
     
  11. keritto

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    did you meant that on rv770 marked up die shot ... it's L2 cache
     
  12. nAo

    nAo Nutella Nutellae
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    Keritto: nice picture but I didn't know LRB had ROPs :)
     
  13. Jawed

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    I know the dimensions of the dies and the physical part of GDDR interfaces prolly doesn't change much in size with varying process - dunno how shaky that assumption is... Not sure how much the interface type would affect the physical size.

    I had similar ideas...

    I think the annotations on that picture are badly mistaken. e.g. QPI and networking are unlikely as this is a graphics chip not a co-processor. There's no fixed function RBEs (just texture decompression/filtering + texture cache) and the display stuff is more likely to be in the bottom right corner, I reckon.

    Jawed
     
  14. fellix

    fellix Hey, You!
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  15. Jawed

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  16. keritto

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    That's weird. I'm tottaly not tracking that with mesuring die parts but why they couldnt shrink memory interface from 90nm(G80)->65nm(GT200) for example. I think they didd so they decide then they could have a wider bus. From my point of view they even have troubles producing 384-bit bus @90nm while 448-bits are pretty plausibe @65nm on nV chips as we all could see.


    Well I agree on RBEs there should be any according to what intel says since it start with RT BS story, but i just added RBEs for sake of my conscience cause something will need to composite it all together. Anyway thats my way of connecting old with new. But graphic chip:?: No way larrabe is graphic chip :lol: it's just multicore CPU that will be oriented to conquer last segment of PC market that still isn't in intels pocket. So it'll need some bus and intel gave away standard FSB for QPI with Nehalem last year as we all know. So it's THE BUS.

    As display goes i think that interface "Display is going all the way on the left side where i put it just didin't wrote twice and that lighter stuff is TMDS ... no way that all display "RBE" could be that small

    @Felix

    Only quad 64-bit whatever interface?? Did you meant 256-bit gddr5? Well maybe but intel is no way so "market narrow" if this is really 600mm chip it should be paid off multi-way with maybe only 12 cores working in some market segment. They'll sell all crap that they produce :sad: why waste it when you can sell it.
     
  17. fellix

    fellix Hey, You!
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    Not really.
    The Nehalem phy interfacing is quite different, as it includes additional ECC pads (one group for each channel), at least.

    p.s.:
    By the way, the memory pads are very conveniently placed on the opposite ends of the ASIC, not surrounding the die, very similar to the Cell/B.E. arrangement. That way, the whole IC would scale a bit better with the advancement of the manufacturing process, as the interfacing logic often doesn't scale well enough with the rest of the chip.
     
    #57 fellix, May 15, 2009
    Last edited by a moderator: May 15, 2009
  18. Arun

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    Jawed, how did you calculate the 54mm for Larrabee's DDR pads? Did you perhaps use the pics on the first page which were truncated? Because I get something more like 70mm+ than 54mm personally - which would imply 512-bit GDDR5, imo, which makes sense for that die size.

    Of course, it'd also nicely imply that the "our bandwidth efficiency is way better than anybody's else!" claims were, to put it nicely and in terms even a bankrupt banker could understand, mark-to-model fantasy. Or this is yet another R600-like bandwidth overshooting. Heh.
     
  19. Jawed

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    I used this picture:

    http://www.pcgameshardware.de/aid,6...127811&article_id=683939&page=1&show=original

    I don't see truncation there. Perhaps you can explain?

    I'm treating the physical part of the DDR as being almost the entire length of the two longest sides of the chip. It doesn't fill either length and since those sides of the chip are somewhere in the region of 28-31mm :?: it seems to me the DDR is somewhere just short of 60mm in total. I get a range of 54-58mm.

    Of course, it would be funny if this is a die-shot of a 32nm Larrabee and the whole thing is considerably smaller than that earlier wafer shot indicated :lol:

    Jawed
     
  20. tangey

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    Can we please stick to the "why did the chicken cross the road jokes" ?, I never seem to get those fixed-function rasterisation jocularities

    :)
     
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