Larrabee Die-Shot - Analyze this

CarstenS

CarstenS

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Today, intel showed the first detailed die-fotograph of Larrabee - some pictures are to be seen at PC Games Hardware.

http://www.pcgameshardware.de/aid,6...erten-Die-Shot-vom-Larrabee/Grafikkarte/News/

Some of the functional units can be distinguished also - pleases take your guesses as to their respecitive number now. ;)

Some photoshopped versions of the pics are soon to follow in the image gallery:

http://www.pcgameshardware.de/aid,6...ge_id=1127576&article_id=683939&show=original

I really hope I#ve not been living under a rock the last couple of months and this is really something new.
 
I don't know much about how hw structures look on a die shot but this seemed fairly obvious:
20iv3oj.png
 
What looks like the GDDR interface is interesting as there's so much of it. If the die is 30x20 (which I think is a bit small) then that means the DDR interface is about 54mm.

The 256-bit GDDR5 on RV770 is about 36mm. The 512-bit GDDR3 on GT200 is about 75mm.

Larrabee has a 384-bit bus? GDDR3?

Jawed
 
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V3 said:
Is Larrabee going to be competitive with 8 texture units ?
Click to expand...
Assuming they're quads, that's 32. The clock is the real killer question.

Larrabee should have the best overdraw reduction (other GPUs' early Z rejection is coarse-grained and so conservative).

Dunno, at 1GHz it doesn't seem likely.

Jawed
 
One more, because photoshop is fun.
2hcdzja.png


If the green blocks are texture units, then what are the blue ones? They are strangely asymmetrical.
 
Blue ones for bus<->memory?

One thing I'm wondering is if Intel has built the DDR interface in two parts, GDDR3, say 256-bit and GDDR5, 128-bit. Rather than trying to make the interfacing multifunctional.

Or, maybe it's 256-bit GDDRx + 128-bit "communicate with another Larrabee"?

Jawed
 
The x86 cores are very Atom-like in shape. The L2 array can definitely be spotted in the one end of the tile, and in the opposite end there is also some uniform array of structures (registers ?).
 
The cores are more svelt than my guesstimated lower bound of ~18mm2.
It's what, 15 or so? I unfortunately don't have time to do more than glance.

At 32 cores, Larrabee would have two short-linked rings of 16.
Other statements said that the bus was routed over the L2.
The odd part is that the caches don't really point to a very even distribution.

The four blue sections would fit with the desire to space memory controller ring stops evenly, and they could also be used to serve as the connection points that connect the two rings.
 
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