Larrabee Die-Shot - Analyze this

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Silverthorne die (Atom) in a LRB disguise -- minus half the L2 and the AGTL+ interface.
Imagine the SIMD unit for yourself! :D
 
Jawed said:
What looks like the GDDR interface is interesting as there's so much of it. If the die is 30x20 (which I think is a bit small) then that means the DDR interface is about 54mm.

The 256-bit GDDR5 on RV770 is about 33mm. The 512-bit GDDR3 on GT200 is about 75mm.

Larrabee has a 384-bit bus? GDDR3?

Jawed
Click to expand...

Has it been confirmed Larrabee is using GDDR? I recall rumors of Intel being intrested in XDR2 and using their own fabs to make it.
 
Nice shot. I wonder what the orange part of the chips does, it's a 1/3 of the chip (more or less..)
 
The orange part probably encompasses ROPs, memory controllers, command processor, other controller logic.

I refined my guess somewhat with regards to core area from the Larrabee shot, with about 2/3 of the die taken up by the x86 cores themselves.
If the chip is 600 mm2+, it puts the cores in the neighborhood of 12-13 mm2, though the error bars on this crude estimate are pretty wide.
 
Command processors, tesselators? Erm its got like 100 x86 hardware threads, you think it may be able to handle commands without custom silicon?

My god what if they have to give up a whole PC for it!, 4Mhz 8088 PC running dos tho :p
 
DeanoC said:
Command processors, tesselators? Erm its got like 100 x86 hardware threads, you think it may be able to handle commands without custom silicon?

My god what if they have to give up a whole PC for it!, 4Mhz 8088 PC running dos tho :p
Click to expand...
We're talking about the swathe of die in the RV770 review on TechReport that's coloured orange :???:

Jawed
 
Jawed said:
We're talking about the swathe of die in the RV770 review on TechReport that's coloured orange :???:

Jawed
Click to expand...

Ahh phew thought the world had gone mad for a bit, but nope it was just me not paying enough attention sorry :D
 
From the old slides they were planning for DDR3, FBD and GDDR of some sort. I remember 128 GB/s as a number they were throwing around on the early spec. And they were aiming for 1.7 to 2.5 GHz for clock. These one is 32 cores, they were throwing around number for 16 to 24 cores previously. So I think the 16-24 cores die size will be more reasonable than this version.
 
8MB of L2 cache - it's a hell of a lot. It's interesting how innocuous it looks on that die shot.

The TUs appear to have a huge amount of cache, too. It's curious it looks much darker. Could that be indicating the associativity and more complex banking of the core's L2, i.e. "less dense with memory" having more non-memory logic?

512KB of cache per TU? 1MB?

Jawed
 
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