How can LRB have a 'stock' clock, when there are no SKUs?
If something is overclocked, as the 1 TFLOP demo was stated as requiring, I assumed there was some base clock to go over.
You're missing my point. I think they probably would have traded off density for better power consumption.
I suspect that would have been secondary to the convenience (necessity?) of trying to get a pipeline first designed to run at ~200 MHz to the 1.5-2 GHz range.
I also don't think it necessarily means breaking TDP. Depends on your cooling. If you cool well, you lower Tj and your transistors run cooler, consume less power, etc. etc.
The range of cooling solutions for the target market is what it is. Perhaps as a boutique product, Intel could have afforded to splurge for Larrabee more so than either Nvidia or AMD do, with Fermi being perhaps the highest class stock cooler and most generously expanded case requirements in quite some time.
Penryn hit markets in late 2007. If LRB hit markets in late '08 (which would have taken a miracle) it probably would have been much better. They would have had a density advantage, a performance advantage, a big power advantage (HKMG + normal process shrink gains) and perhaps, just perhaps, those two advantages could make up for other issues.
RV770 was released in mid '08 and it was denser than the Larrabee that was put on display. It was barely edged out by the overclocked Larrabee in SGEMM.
I would have been curious how the 600mm2 chip would have performed, given its 2.5x die size advanage.
However, that's clearly impossible scheduling wise. A more interesting questions is: What if they skipped 45nm and went straight to 32nm at the end of 2010? Again, while their competition is still on 40nm. They'd have a half-node density advantage, mature yields, a substantial transistor performance advantage, etc.
The point is that Intel should have figured out how to leverage their process technology advantages more heavily (to make up for software disadvantages), rather than falling victim to an overly aggressive schedule and coming to market at parity.
Is this more of political and product-based question?
The product lines with first dibs on the leading edge processes did not seem particularly interested in Larrabee coming to the party. The latest anouncement of an HPC initiative including Larrabee is actually a change of pace, since Intel or one portion of it had ruled that out earlier. The proposed socket version of Larrabee was ruled out by one of the execs linked with the Xeon lines.
It would make sense, the idea of a 600mm2 chip sold for less than a fraction of a high-end Xeon with 5-10 times the performance for certain workloads would give Intel's high-margin lines a headache.
It's possible that the demo version merely had 16 cores enabled.
My interpretation of the spokesman's statements was that this was not the case.
Yet it appears to be quite important as the basis of quite a few "forward looking" multi-core projects.
Mostly the ones where the core itself is secondary to the primary focus of the design, or perhaps the project was not really high enough priority to warrant the resources to make a new one.
For this latest project, it is the messaging network.
For Larrabee, it was the VPU and cache, and I always got the subjective impression it did not rate that highly (Intel's schizophrenic raytracing/rasterizer statements, high end-no volume-no I mean high end target market, the wandering target performance level, the use of a core at clocks way above its original design envelope).
Maybe it was a "too simple to fail" ethos?
As far as the first product is concerned, maybe it was more of a "do enough to just get it working but not enough to make anything else we make money from look bad" ethos.
