caboosemoose
Regular
Intel resurrects the Pentium MMX for Larrabee
- Thread starter caboosemoose
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No fixed-function graphics hardware?
I don't know if Larrabee is going to have that much extra computational power to make it competitive with rasterizers if it tries to emulate everything.
I don't know if Larrabee is going to have that much extra computational power to make it competitive with rasterizers if it tries to emulate everything.
Funny how as we need to develop newer and better technology that we discover the old tricks ended up being better...
Core 2 Duo has it's basis loosely in the P3 architecture, now the next order of magnitude performance upgrade will be based on the "P1" architecture. Cool IMO
Core 2 Duo has it's basis loosely in the P3 architecture, now the next order of magnitude performance upgrade will be based on the "P1" architecture. Cool IMO
It's more like mass quantities of some old tricks work better than fewer new tricks in certain situations.
It's also not likely to be all that old.
Intel's learned a few things since Pentium MMX, and if it weren't for the new vector engine, Larrabee would be very uncompelling.
It's also not likely to be all that old.
Intel's learned a few things since Pentium MMX, and if it weren't for the new vector engine, Larrabee would be very uncompelling.
It would be an overstatement to say that they are just dusting off the Pentium MMX. At the circuit level, a good amount needs to change.
The vector engine and hopefully x86-64 support mean the FPU, register file, and decoders will be redone.
The threading means the scheduling will be redone.
Load/Store might need work due to the increased traffic to the caches.
The integer side doesn't really need to change as much from a unit perspective.
Many of the higher-level details would most likely be very similar, because it's not really worthwhile to change anything.
There's really not much you can add to Pentium MMX that wouldn't detract from the point of having Larrabee, which is that each individual core is less important than the system in place to feed a large number of them.
That being said, it's too early to be certain what they're doing. The details are too sparse.
I can see the appeal of the idea, though.
The vector engine and hopefully x86-64 support mean the FPU, register file, and decoders will be redone.
The threading means the scheduling will be redone.
Load/Store might need work due to the increased traffic to the caches.
The integer side doesn't really need to change as much from a unit perspective.
Many of the higher-level details would most likely be very similar, because it's not really worthwhile to change anything.
There's really not much you can add to Pentium MMX that wouldn't detract from the point of having Larrabee, which is that each individual core is less important than the system in place to feed a large number of them.
That being said, it's too early to be certain what they're doing. The details are too sparse.
I can see the appeal of the idea, though.
Well, saying Larrabee is like the Pentium MMX is about like saying the Pentium-M is like the Pentium 3.
Sure, they have a good shared lineage to be sure, but the architecture isn't the same at all. I always hated hearing people say "Well it's basically just a P3 with a few minor boltons", when in reality it wasn't -- for all the reasons you just described.
But still, it's interesting to me that we're going back to the "old days" for some lessons in how to do things the Right Way (TM).
Sure, they have a good shared lineage to be sure, but the architecture isn't the same at all. I always hated hearing people say "Well it's basically just a P3 with a few minor boltons", when in reality it wasn't -- for all the reasons you just described.
But still, it's interesting to me that we're going back to the "old days" for some lessons in how to do things the Right Way (TM).
That's why I said it would be an overstatement, in the sense that it is an overstatement to say the relationship is that close.
Whether it is the Right Way is highly dependent on what it is you want it to do.
If it were the Only Way, Gesher wouldn't be coming out alongside it.
I was just clarifying that I understood the difference
I understand that too. But look at the bigger picture -- Intel's best performing (power/watt, performance/price) architecture to date is based on a technology they abandoned more than eight years ago. And now their future awe-inspiring modular processor will be based on technology they threw out bordering on 15 years ago.
I find humor in that
No worries there, and sorry I've not been around much this last week or two. Keeping my head down, busy busy busy.
As for what I think.....I'll save that for some coming editorial
Well, the P-M did show up as a P6+++ in cpuz. And it seemed to be mostly a p3 with an overhauled cache and memory system.
Larrabee seems to have less in common with the P-MMX than the P-M did with P3 though.
Except you can say that P4 was also based off of P3. The P6 core may have had some lineage to the P-MMX as well.
To me the article seems incredibly vague.
The only point I got, was that Intel are moving away from an out-of-order(OoO) architecture because it costs too much space and money. Can someone tell me is this the result of a lack of technological advancement in developing OoO architectures or lack of experience? I find it difficult to believe that an in-order(Io) architecture will be more efficient, especially when it comes to things like branching.
The only point I got, was that Intel are moving away from an out-of-order(OoO) architecture because it costs too much space and money. Can someone tell me is this the result of a lack of technological advancement in developing OoO architectures or lack of experience? I find it difficult to believe that an in-order(Io) architecture will be more efficient, especially when it comes to things like branching.
Killer-Kris
Regular
Where do you get the idea they're moving away from OoO for anything but this?
More than anything it's probably just an attempt to target a different workload, not a shift in overall design philosophy.
It won't be but I very much doubt anyone is expecting it to.
Mintmaster
Veteran
Modifying a Pentium MMX doesn't seem like a bad idea to me. Discounting the effects of instruction set like SSE, Pentium III wasn't a whole lot faster per clock (maybe 20-30%?), and considering the drop from there to P4's IPC, I would guess that Core 2 has around double the IPC.
I'm sure that bringing the Pentium MMX up to a few gigahertz will lose some IPC, but throw in some instruction set additions and maybe some tricks they've learned over the last decade, and they could probably close that gap a bit.
Even at, say, 60% of the Core 2 IPC they'd be doing pretty well. Probably better than the in-order efforts of IBM and Sony, I think. I really do wonder how different the workload will be for Larrabee compared to that faced by ATI/NVidia in the DX10 world. GPUs are incredibly efficient at what they do compared to CPUs.
5 times the transistors for an "efficient" core means 5x fewer cores. The Pentium MMX wasn't that slow.
I'm sure that bringing the Pentium MMX up to a few gigahertz will lose some IPC, but throw in some instruction set additions and maybe some tricks they've learned over the last decade, and they could probably close that gap a bit.
Even at, say, 60% of the Core 2 IPC they'd be doing pretty well. Probably better than the in-order efforts of IBM and Sony, I think. I really do wonder how different the workload will be for Larrabee compared to that faced by ATI/NVidia in the DX10 world. GPUs are incredibly efficient at what they do compared to CPUs.
Efficient as in perfomance per clock or per mm2 of silicon? For parallel machine like Larabee, the latter is all that counts. 4.5M transistors for a Pentium MMX core is pretty damn efficient compared to ~50M per core (non-cache) in Core 2 Duo. Granted, there's a lot of SSE3 hardware there, but that's still an enormous difference.
5 times the transistors for an "efficient" core means 5x fewer cores. The Pentium MMX wasn't that slow.
I don't know from what vantage point P4 looks like it was based on P3.
It did everything differently than the P3.
It didn't decode the same way, predict branches the same way, do register renaming or OoO the same way, didn't execute instructions in the same way.
What exactly did it do that was the same as P3?
You beat me to the punch, so... yeah. The P4 architecture (netburst) was considerably different than the P3 architecture, for at least all the reasons you mention.
As for going back to an in-order processor design for Larrabee, I think it makes sense... Remember that we're ultimately talking about a 'stream' processor, so massively parallel in-order makes sense IMO.
The individual cores will be slower than a single one with OOO. But they target a different workload: if you have to go multicore/multi-threaded anyway, it makes a lot of sense to go for the fastest possible sustained throughput for the whole chip.
Sure, any single-threaded app will be blown away compared with the performance on a single OOO core, but the performance possible for a good multi-threaded app will be much higher if you only focus on throughput and replace all the stuff that increases single-threaded performance with more cores.
Rainbow Man
Veteran
Surely the difference has to be more than that. P3 had a very very fast on-chip L2 (256 bits wide) while pentium used direct-mapped cache on the motherboard I remember.
Floating point was also vastly faster on the PPro and up.
Btw. Why would Intel chop up and rebuild a P-MMX? There'd be no need for it to be x86 compatible in such a specialized situation. Surely rebuuilding a chip tailored for the task with an inxtruction set better tailored would be more ideal. Pentium only has 8 registers to play with after all that's pitiful today.
We probably miss a large piece of the big picture here I think because what we know now doesn't make much sense to me.
Peace.
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