Intel, Integrated video and Eurasia

[arjan de lumens]

The apparent 4GHz wall of Intel processors is AFAICS caused mainly by heat/power consumption, not fundamental limitations of execution units or clock distribution (Intel has demonstrated a 10GHz ALU before, and the Prescott has a clock skew of about 7ps across the chip), and as such it just demonstrates my point: that increasing pipeline length to increase clock speed unavoidably also dramatically increases power consumption per instruction/operation.

 

[Simon F]

The main problem with designing GPUs for very high clock speeds, other than design effort/time, is that to support the higher clock speeds, each pixel has to pass through a larger number of pipeline steps, causing the power consumption per rendered pixel to increase almost linearly with the targeted clock speed of the chip.

It's actually much worse than that.

1. To achieve a higher clock speed, you typically also have to increase the voltage, and power increases with the square of V.
2. Secondly, AFAIK, if you increase the clock speed by a factor of Y, you need a more than Y factor increase in the number of pipeline stages.

IMHO, it's better to run more slower tasks in parallel.

 

[KimB]

One thing that you may have noticed is that most processors have relatively small changes in power consumption across a fairly wide range of frequencies. Once you get the clock frequency up to a certain point, however, the power consumption starts to skyrocket. What I'm suggesting is that a large portion of the clock frequency at which this turnover lies depends upon the engineering of the core (though obviously there are physical limits that cannot be shoved aside with any amount of intelligent engineering).

 

[MfA]

It's actually much worse than that.

1. To achieve a higher clock speed, you typically also have to increase the voltage, and power increases with the square of V.

1. Still, even at the low power end Intel's circuitry tends to be a tad more sophisticated than what is commonly found in GPUs. They get over twice the clock of GPUs with a lower voltage. Of course both their tools are almost certainly better (patents have had a wonderfull effect on innovation in the market of asic design software) and a huge amount of their work goes into full custom design.

 

[arjan de lumens]

To achieve a higher clock speed, you typically also have to increase the voltage, and power increases with the square of V.

True if you already have a physical chip in front of you and just want to clock the hell out of it; however at the design phase you can always raise the clock speed without raising the required supply voltage by just reducing the amount of logic between your pipeline stages.

Secondly, AFAIK, if you increase the clock speed by a factor of Y, you need a more than Y factor increase in the number of pipeline stages.

True. But on the other side, the per-cycle power consumption of the logic between the pipeline stages is fairly constant, which is why I said that power consumption per pixel would increase 'almost linearly' rather than 'superlinearly'.

One thing that you may have noticed is that most processors have relatively small changes in power consumption across a fairly wide range of frequencies. Once you get the clock frequency up to a certain point, however, the power consumption starts to skyrocket. What I'm suggesting is that a large portion of the clock frequency at which this turnover lies depends upon the engineering of the core (though obviously there are physical limits that cannot be shoved aside with any amount of intelligent engineering).

What processors might those be? There appears to be many cases where official TDP is kept constant over a large range of clock speeds but actual power consumption is not.

Tomshardware clocked an AthlonXP down until it wouldn't go further and found almost perfectly linear power consumption down from ~2GHz to 300 MHz. PentiumM (dothan core) is even better: halving its clock speed from 2Ghz to 1GHz reduces its power consumption from 21 to 5 watts.

 

[KimB]

Linear is a relatively small change in power consumption, as far as I'm concerned. It means that the switching of the transistors is the primary mechanism of power consumption. What I'm attempting to claim is that most high-end chips today are running out of this linear region, and this is a major reason for their high power consumption.

 

[arjan de lumens]

Linear is a relatively small change in power consumption, as far as I'm concerned. It means that the switching of the transistors is the primary mechanism of power consumption. What I'm attempting to claim is that most high-end chips today are running out of this linear region, and this is a major reason for their high power consumption.

AFAIK, when high-end chips run out of the linear power consumption region, it is usually because the chip vendor has hit the inherent design clock speed of the chip and tries to overcome it by cranking up the supply voltage, which causes roughly n^3 power consumption (one n from clock speed multipled with n^2 from the voltage bump, assuming that max clock speed is roughly proportional to voltage). Not quite sure if this has happened to Prescott, though - when the vendor cranks up voltage this way, you usually get a chip with crappy overclocking potential, and IIRC Prescott doesn't seem to have that problem.

This is however a rather separate problem from what I've been trying to point out, which is that by increasing the design clock speed - by adding flip-flops for an increased number of pipeline stages - the power consumption per operation increases greatly. And this definitely has happened in the Northwood->Prescott transition.

 

[KimB]

That's all well and good, but Intel doesn't appear to have been terribly concerned with power consumption of the P4 core (to their cost). Here's my claim as to what is going to happen:

1. Clock speeds are going to stabilize at around 3GHz for CPU's within the next two years. Future increases in CPU performance will revolve around small efficiency improvements and greater numbers of cores, with differing clock speeds for the different parts depending upon the market.
2. CPU's will become more parallel, with a move towards Cell-like architectures in the next 5-10 years. This will lead to a greater logic density with respect to cache density.

3. GPU's will become more general, requiring more cache for efficient operation. Their instruction set will solidify, making changes much more sowly in the future, giving manufacturers more time to work on ways to increase the clockspeed of the parts. GPU's will, in 5-10 years, stabilize at 2-3GHz.

 

[Ailuros]

Their instruction set will solidify, making changes much more sowly in the future, giving manufacturers more time to work on ways to increase the clockspeed of the parts. GPU's will, in 5-10 years, stabilize at 2-3GHz.

Still too optimistic for my taste, both on the frequency as the expected timeframe.

 

[MfA]

PentiumM (dothan core) is even better: halving its clock speed from 2Ghz to 1GHz reduces its power consumption from 21 to 5 watts.

In other words superlinear ... not the greatest way to back up your point