IBM to produce Nvidia chips

[Dio]

Cool. They're dead by the end of the year, but I still can't get one from Scan if I want to... that's a hell of a shelf life.

 

[DegustatoR]

I think dave was speaking about the RV350

I understand that. I was just wondering: what are ATI waiting for if they already have final chips on their hands?..

Any chance we'll see NV36 announced at the same time as NV35?

NV35 - may
NV36 - june
For now they are...

 

[MuFu]

I think dave was speaking about the RV350

I understand that. I was just wondering: what are ATI waiting for if they already have final chips on their hands?...

Could be lots of reasons not directly related to bad yields/problems...

-waiting to build up a stockpile of enough low-percentile ASICs to supply non-Pro demand
-allowing NV34 & NV31 to go up against the 9500 Pro in reviews (whereby ATi kick booty)
-waiting until the OEM channel is mostly purged of 9500s (then AIBMs can eat up the rest of the inventory)
-evaluating NV31 & NV34 in order to determine final RV350 clockspeeds
-capacity issues at the fab

Notice that we haven't seen much of the 9200 either - there can't be any problems with that (logistics aside), can there?

NV36 should require only a fairly short R&D since it is based on relatively small changes (I suspect it the logical equivalent of "half" an NV35 + the NV31 memory controller). NV40 I don't think will be ready until next spring - there's some stuff starting up in Sept/August kinda timeframe which would be indicative of *at least* a 3 month TTM from then on. All IMHO, of course.

MuFu.

 

[Dave Baumann]

-waiting to build up a stockpile of enough low-percentile ASICs to supply non-Pro demand

I think this is likely to be the case. I'm still waiting to see whether or not they are going to A13.

Notice that we haven't seen much of the 9200 either - there can't be any problems with that (logistics aside), can there?

Don't bet on that one! 9200's are OK, 9200 PRO's aren't quite right yet...

NV36 should require only a fairly short R&D since it is based on relatively small changes (I suspect it the logical equivalent of "half" an NV35 + the NV31 memory controller).

NV36 is 4x1 then?

 

[LeStoffer]

NV36 should require only a fairly short R&D since it is based on relatively small changes (I suspect it the logical equivalent of "half" an NV35 + the NV31 memory controller).

NV36 is 4x1 then?

And NV35 is 8x1 then?

 

[MuFu]

Notice that we haven't seen much of the 9200 either - there can't be any problems with that (logistics aside), can there?

Don't bet on that one! 9200's are OK, 9200 PRO's aren't quite right yet...

So clockspeed/yield related? I assume they aren't based on different cores.

NV36 should require only a fairly short R&D since it is based on relatively small changes (I suspect it the logical equivalent of "half" an NV35 + the NV31 memory controller).

NV36 is 4x1 then?

Well I understand it is a 0.13u ASIC, uses DDR-I, was drafted very rapidly as it became evident that NV31 wouldn't be capable of 450MHz, performs somewhere between the NV31 and NV35 and is suitable for a mobile implementation. A 4x1 architecture at 350-450Mhz would make sense. No news of a tape-out though, you notice... :?

MuFu.

 

[elroy]

Any ideas on why they would be releasing the NV36 so soon after NV31? Is it just to allow an increase in clockspeed? Or does the NV31 have similar hardware bugs to NV30? All these products coming out makes my buying decision so much harder - NV35 will probably be $1000 down here (Oz), though I don't know if I can hold out till July/August, which is when I'm guessing we'll see NV36. I need to get rid of this GF DDR, goddammit!

 

[RussSchultz]

I've heard some interesting info about .13u at TSMC (though I think some of it is confused)

-Yeild is now very good (better than .18u)
-.13u cost is 20% cheaper per transistor than .18u
-TSMC only offers low-k w/copper
-IBM is very small portion of NVIDIA wafers
-NVIDIA is TSMC's largest customer
-All of NVIDIAs production is in .13u now (I think this is wrong)
-A run rate of 10k wafers per month. (This may be 1k, I can't remember correctly)
-There is tremendous capacity at .13u, with all of the .13u fabs coming online (in hopes of a financial upswing)

 

[Pete]

Don't bet on that one! 9200's are OK, 9200 PRO's aren't quite right yet...

Is this because, IIRC, ATi moved production from TSMC to UMC? Can another fab have that much trouble producing a proven chip on the same process, or are ATi pushing core clock-speed limits?

 

[asicnewbie]

RussSchultz
> -[TSMC 0.13] Yield is now very good (better than [TSMC .18u])

This statement needs some context. Nevertheless, I assume this statement compares TSMC's 'general' logic process (not low-power, not low-voltage.) Yield rates are difficult to calculate. Someone showed me a bunch of tables and formulas TSMC gives to its customers. Using the tables, you can 'estimate' your design's expected-yield rate, based on what process-features (RAMs, logic, # metal-layers, etc.) the design uses. (RAMs are still yield killers on just about any process.)

Pete
> Can another fab have that much trouble producing a proven chip on the same process

well that's the thing. TSMC and UMC are physically different production lines, with different process characteristics. Even moving a design from 1 line to a different production line (both running the same foundry recipe) within the same building can cause yield changes! (In a well-maintained foundry, differences should be *minimal.*) The fact that a design has been 'proven' at TSMC (or UMC), has no bearing on another company's foundry process. They use different materials, formulas, equipment, etc. I suppose if they were physically identical in every way, then the transfer would have no risk.

There is one thing working to ATI's advantage. TSMC and UMC have very similar overall 'design-flows.' (from Verilog source-code all the way to 'tapeout') ATI must re-run the back-end (synthesis, gate placement, interconnect routing, parasitic timing extraction, etc.) each time they target a different foundry-process. In ATI's case, TSMC and UMC are supported by the same CAD tool vendors (Cadence, Synopsys, but I'm guessing ATI use specialized tools from others, too.)

So if TSMC and UMC cell libraries are similar enough spped/performance-wise, ATI might not even have to make any design-changes, just 'recompile' the chip for the new process.

...

Why is a similar 'design-flow' so helpful?

Let's pretend ATI were to re-target a UMC design for IBM. As far as I know, a lot of steps in IBM's back-end design-flow require proprietary IBM software, or customer-handoff to IBM's internal engineering teams. Basically, ATI's engineers can't use their own (familiar) design-environment, they have to either handoff some work to IBM's crew (and cross their fingers!), or import/learn/debug a new IBM software package. Imagine writing a library-DLL in C, and then having to rewrite it in Pascal because your customer asked you to (Thanks to IBM's new focus on their foundry-business, IBM is exposing more of their design-flow to third-party CAD tools, but it remains to be seen if this 'shift' from internal to third-party really works. My guess is that most potential customers will wait for IBM to demonstrate succsesful tapeout on a chip-designed with COT (customer-owned tooling), before signing-off on a multimillion dollar prototyping run.)

 

[DegustatoR]

Could be lots of reasons not directly related to bad yields/problems...

Right. But my sources is speaking about "some problems" w/R(V)350 on 0.13um. That's why I said "problems"

NV36 should require only a fairly short R&D since it is based on relatively small changes (I suspect it the logical equivalent of "half" an NV35 + the NV31 memory controller).

Yes, it looks like half-NV35: truly 4x1 in all situations (though both of them should still be able to dynamically reconfigure themselfs), at least x2 faster PS2.0 calculations plus considerably higher clockspeeds comparing to NV31.

NV40 I don't think will be ready until next spring - there's some stuff starting up in Sept/August kinda timeframe which would be indicative of *at least* a 3 month TTM from then on. All IMHO, of course.

AFAIK, right now they want to show it at Comdex'03 (as they always did in the past, BTW ). As for retail time - that is remains to be seen.

 

[asicnewbie]

Well it's not quite a straight 'ASIC foundry' deal, but it looks like Intel is going to collaborate with Emulex on some storage (Serial SCSI, Serial ATA, Fibre Channel) processors.

http://www.eetimes.com/semi/news/OEG20030415S0039 - "Intel, Emulex team up on 90nm storage processors"

Perhaps Intel is inching closer to the ASIC-foundry business?

[Heh, I still stand by my original statement -- that Intel's still unlikely to join to the 'ASIC foundry' business-model in the traditional sense. According to the eetimes article, current the Intel/Emulex agreement indicates join-development and joint-ownership of the final products...definitely a departure from the usual 'cash per fabbed wafer' contract!]