IBM tips Power6 processor architecture at ISSCC

[Megadrive1988]

http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=179100613

SAN FRACISCO — At the International Solid-State Circuits Conference (ISSCC) here, IBM Corp. tipped its next-generation Power6 processor architecture for servers.

In various papers at the event, IBM indicated that the Power6 is a 65-nm processor that operates in excess of 4-GHz. Built around silicon-on-insulator (SOI) and other technologies, the Power6 is the follow-on processor to the company’s current Power5 architecture.

In one paper, the company described a 5.6-GHz Power6 processor with 64-Kb of Level 1 data cache. The processor is said to have an eight-way, set-associative design with a two-stage pipeline supporting two independent reads or one writes per cycle.

IBM also makes use of a 5-GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 microns wide and 1.2 microns thick.

In another paper, IBM described low-latency fixed-point and binary floating-point units for the Power6. The floating-point unit incorporates “many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cyle, 13-FO4 pipeline,â€￾ according to the company’s paper.

The Power6 design uses dual power supplies, a logic supply in the 0.9-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.

 

[suryad]

WOW! 4 ghz!! I cant wait to see numbers on that baby!

 

[Rolf N]

I wonder if Apple is going to feel silly

 

[Sonic]

Why would Apple feel silly? They could always decide to go back to IBM at a future point in time. Who says they will do away with universal binaries?

 

[pc999]

I dont want to start a Rev thread, if it take that direction I am sorry in advance, but once that there is the rumor that IBM had show the/a variation of the Rev CPU to Apple and they refuse it do you think that there is any chance of being a variation of this PPC6 (this low latency/good fp(?) sounds good for for a console)?

What do you think?

 

[karlotta]

I wonder if Apple is going to feel silly

I dont believe Apple left IBM for intel because of the slower cpus, They left IBM because Apple is allabout lowgrade parts in a highgrade manufacturing. Intel is cheaper. That new 4g IBM part will be 2000$ IMO.

 

[pjbliverpool]

I imagine Apple where made aware that this chip was on the roadmap when they were in contract renewal discussions with IBM. I imagine they also has similar big numbers thrown at them aswell so I doubt they will be losing sleep over this announcement. As for its final performance, well thats a while away yet. Somehow I don't see it leaving 2007 AMD and Intel CPU's in the dust.

 

[Rolf N]

I dont believe Apple left IBM for intel because of the slower cpus, They left IBM because Apple is allabout lowgrade parts in a highgrade manufacturing. Intel is cheaper. That new 4g IBM part will be 2000$ IMO.

The official line of reasoning was "performance per watt".
I don't know anything about the pricing situation. That switch is a painful move for the Mac software ecosystem and just a little markup here and there doesn't seem to justify that to me, especially not with Apple, they never were cheap to begin with.
I also can't shed the feeling that IBM must know that a business with thin margins is better than no business at all. Apple was a significant customer.

 

[Megadrive1988]

IBM POWER6 Details Unveiled

Pipelined cache, SOI and 8-way associative L1 cache... the POWER6 is a speed demon and an oddball

Yesterday at ISSCC, IBM hinted a little bit at its next generation POWER6 CPU. The processor is the first from IBM to feature Silicon-On-Insulator (SOI) technology used by AMD since 2004. IBM representatives also claimed the new chip will use a 65nm process running at an astounding 5GHz.

IBM previously revealed that the CPU would feature an 8-way associative 64KB L1 data cache. POWER5 also utilizes an associative L1 data cache. Intel processor architectures opt for direct cache mapping on the L1 cache instead. POWER6 is also unique in the fact that it will use a pipelined cache. This new design allows for two simultaneous reads from the cache per clock cycle or a single write.

IBM has previously revealed that POWER6 will be a 4-issue CPU, meaning four instructions can actually be sent own the CPU pipeline at once. IBM officials did not comment on simultaneous multi-threading (SMT), but POWER5 utilizes two logical threads per core in its current design. There does not seem to be any indication this will change for POWER6.

The POWER6 processor has been under development at IBM (at least publicly) since 2002 as part of the "eCLipz" processor family. The goal of the project has always been to unify all of IBM's RISC architectures under a single chip, thus eliminating the need for a separate architecture on the "e," "i," and "z" series servers.

Expect to see the POWER6 chip in servers in 12-18 months.

http://www.dailytech.com/article.aspx?newsid=670

 

[Megadrive1988]

whoa

http://www.theregister.co.uk/2006/02/07/ibm_power6_show/

IBM thumbs nose at heat concerns, kicks Power6 to 6GHz

The Power6 chip will run between 4GHz and 5GHz and has been shown to hum away at 6GHz in the lab. IBM reckons that some process technology breakthroughs have allowed it to kick GHz higher while still keeping heat and power consumption issues under control. All told, IBM claims that Power6 will be twice as fast as competing server processors from Intel, AMD and Sun Microsystems.

much higher clocks than even CELL, which as of 2005 was meant to be running at 4.6 GHz.

of course we are talking about totally different architectures here.

 

[blakjedi]

The official line of reasoning was "performance per watt".
I don't know anything about the pricing situation. That switch is a painful move for the Mac software ecosystem and just a little markup here and there doesn't seem to justify that to me, especially not with Apple, they never were cheap to begin with.
I also can't shed the feeling that IBM must know that a business with thin margins is better than no business at all. Apple was a significant customer.

Ahhh but MS, Sony and Nintendo will outsell Apple by volume by significant margins... hundreds of millions versus tens of millions.... I'd have done it too...

 

[pc999]

Those are symetric, are they dualcore?

 

[Gubbi]

Those are symetric, are they dualcore?

Power 5 had 2 cores on each die. - And multiple dies on each MCM. What you're seing is likely two dual core CPU dies and two L3 cache dies on a single MCM.

Cheers

 

[Rolf N]

Power 5 had 2 cores on each die. - And multiple dies on each MCM. What you're seing is likely two dual core CPU dies and two L3 cache dies on a single MCM.

Cheers

Agreed.
Looking at the colored die shot, there's a clear two-fold symmetry in the left third~half (processing cores probably) and in the memory arrays to the right (L2 caches). The assymetric splotch of logic at the top could be assorted interface stuff.

 

[Bobbler]

Any mentions of chip size? Transistor counts?

Just curious.

 

[pc999]

Power 5 had 2 cores on each die. - And multiple dies on each MCM. What you're seing is likely two dual core CPU dies and two L3 cache dies on a single MCM.

Cheers

But inst the above (first/color) picture a Power6 here 2 cores shares some L2, isntead of a P5? Or P6 based on P5?

OTjust as a appendix) once that you talk about L3, there are quite a few rumurs about L3 in Rev...

 

[pc999]

Theres are a few links here

More info
http://news.zdnet.co.uk/hardware/0,39020351,39251058,00.htm

 

[Carl B]

whoa

http://www.theregister.co.uk/2006/02/07/ibm_power6_show/

much higher clocks than even CELL, which as of 2005 was meant to be running at 4.6 GHz.

of course we are talking about totally different architectures here.

I'm sure though that Cell could reach 6 GHz and beyond on 65nm, considering it reached 5+ GHz on 90nm in the lab. Still - all that aside, just because IBM can clock it up to 6GHz doesn't mean they will. The article seems to imply that power and heat precautions are being thrown to the wind, but that can't be the case to such an extent that suddenly we're going to have 6 GHz chips running at super-high voltages inside servers.

And I guess that's what it comes down to - I'd love to see a chart with the speeds reached on Power 6 at 'x' voltage.

 

[3dilettante]

IBM previously revealed that the CPU would feature an 8-way associative 64KB L1 data cache. POWER5 also utilizes an associative L1 data cache. Intel processor architectures opt for direct cache mapping on the L1 cache instead.

I am unaware of any modern Intel chips, or any modern performance architectures, that use a direct-mapped data cache. I believe the Pentium 4 has a kind of wonky design where it is in general 4-way associative, except that certain ranges of addresses wind up being direct mapped due to how the chip handles associativity.

POWER6 is also unique in the fact that it will use a pipelined cache. This new design allows for two simultaneous reads from the cache per clock cycle or a single write.

Meh, this isn't particularly new for caches in general, though perhaps new for the latency optimized L1. Neither is having multiple reads from a cache new, though it may be that the pipelined access allows the chip to use a port multiple times per clock cycle.