Sweet, sounds like the article is saying IBM basically figured out how to implement a "L1-cache" for the embedded DRAM block!
I wonder if this this is going to be an "IBM-only" technology, or will IBM license this trick out to other foundries.
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The article doesn't say, but I've been told that 1T-SRAM doesn't require any additional mask processing steps (compared to using embedded-DRAM in the same digital-logic foundry process.) But 1T-SRAM's areal density (#bits/die-area) is slightly lower than conventional embedded-DRAM. On the flip-side, embedded-DRAM's higher transistor-density makes it more sensitive to manufacturing defects.
For large embedded memory blocks (of any type) above a certain size, TSMC recommends the use of repair-RAM cells, in order to compensate for RAM defects. (That's where they add a few extra rows/columns to the memory-cell. During testing, if there are any bad rows/columns, a laser-unit fuses the spare-units into the address-range, effectively replacing the bad rows with the spare ones.) The laser-repair step is an extra-cost for final wafer production.
All the major DRAM vendors (Micron, Samsung, Infineon, etc.) have been using laser-repair for years now.
