I just wrote a pipeline article

Uttar,

I think you've been reading too much into the comments said by PR. Even with shader operations its obvious that there is one FP32 and 2 FX12 units 'per pipeline', however its all semantics how you describe a its operations - what the difference between all 4 pipelines working together to produce one pixel in a clock cycle as opposed to 4 in four clock cycles? Not a lot to the end user.

The pipelines still exist, regardless of the operation.
 
Heh, I say those posts are "karma" for pointing out an excessively word-efficient representation of my statements. :p
 
I think the lesson learnt here should read like this: "optimising the English language is not as easy as optimising pixel pipelines" ;)
 
If a pixel shader in one pipeline gets tied up running a large shader, do all the other pipelines stall waiting for it to complete?

If this is the case would it be possible to make each pipeline operate asyncronously.
 
On the edge of the terminology again...

I would say that in a 'single pipeline' items proceed in linear fashion, but it is possible to have parts of an architecture that allow out-of-order processing (e.g. the reorder buffers on the Pentium 2/3). Whether this creates multiple interconnected pipelines or just allows reordering inside a single pipeline I'm not sure.

Separate but parallel pipelines capable of the same operations may or may not be capable of independent operation. I would probably fall on the side of saying that if forced to operate in lockstep they are all part of the same pipeline.

If accepting this convention, items in one pipeline can overtake items in another pipeline, but this is a simplification - there may be overall synchronising events, often implemented as pipeline flushes. Multiple pipelines and multiple points on the same pipelines may also act as multilpe clients to a single external unit, thereby creating some 'loose' synchronisation.

(This also reminds me that 'granularity' is another important point of pipeline analysis as well as bottleneck analysis).
 
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