I know this. I thought DDR4 drops (as GDDR5 does) the burst chop mode of DDR3 which halves the access granularity (at some expense of bandwidth efficiency as the second part of the full length burst is simply masked). But it obviously still exists also in DDR4. But halving the granularity means that while it may be often tolerable with a 128bit controller (64byte granularity equalling the cache line size, but most situations probably prefer the individual controllers which is also the setting AMD recommends), but with 128Byte granularity for a 256Bit controller performance would take a dive in basically all use cases.That's true, but the option apparently is there as it currently is in all AMD processors (Ganged/Unganged modes).