G70 here we come

[Jawed]

I was under the impression that you can't compare ATI transistor counts and NVidia transistor counts - they each "count differently". I haven't seen an estimate of how much impact this has on a comparison, but it seems fruitless to try to use a comparison of the competing IHV's released products. Certainly the difference in die area between NV40 and R420 doesn't seem to warrant the wildly different transistor counts associated with them.

This amounts to 39% more transistors in NV40 compared with R420, versus a 2% difference in area - 220 versus 160 million transistors against 287 versus 281 mm squared.

------------

As to the multi-core thing, well I'll just throw my multi-GPU Xbox 360 theory in for laughs. Hahahaha

Jawed

 

[wireframe]

Except SLI doesn't give two GPU's access to the same memory interface or PCI Express bus.

Beyond that, you would not want to run a dual-core chip in SLI mode. It'd be prone to horrible inefficiencies.

Right, but the current incarnation was obviously designed for greater latencies and discrete boards and such. I was speaking in principle and I should have pointed that out. Neither am I saying that this scaled down version of the current SLI should be then SLIed on a video card scale. But...should you operate closer as a two-core-per-package allows you can get away with some more things that the current implementation cannot. Maybe I am too optimistic in every direction, but I think the current SLI is a planned technology with a future. Not all of the goodies are going to be served immediately. The milking and refining of the technology must be done.

Perhaps we should consider the Asus dual 6800 Ultra and Gigabyte's dual 6600GT when thinking about this.

On a related note, did anyone else find it interesting that Asus said that they expect that board to be the top of the line even after the release of the R520 boards? I found that a strange thing to say for a company selling both.(read that in Xbitlabs Cebit coverage)

 

[psurge]

A "quad", even if processing both vertices and pixels, is still (IMO) very far from being an entire "core". Please correct me if I'm wrong, but I assume there are some significant portions of the chip that are not replicated along with quads: clipping, rasterization, pre/post vertex shader caches, pixel/vertex to "quad" dispatch, global control logic, PCIe interface... come to mind.

 

[Geo]

This amounts to 39% more transistors in NV40 compared with R420, versus a 2% difference in area - 220 versus 160 million transistors against 287 versus 281 mm squared.

Huh? That 2% number is news to Dave Orton. . .

As to the "counting differently" thing. . .I don't buy it. As I recall that was some otherwise sane and responsible spokesman having "a bad speculation day" and has never been proven or re-asserted by responsible authority since. If you read the Orton interview they were head-scratching in early days over it and did (in my view) a little too much of it in public. Be interesting to know if they ever got to the bottom of it to their own satisfaction.

 

[DegustatoR]

A "quad", even if processing both vertices and pixels, is still (IMO) very far from being an entire "core". Please correct me if I'm wrong, but I assume there are some significant portions of the chip that are not replicated along with quads: clipping, rasterization, pre/post vertex shader caches, pixel/vertex to "quad" dispatch, global control logic, PCIe interface... come to mind.

That's because there's no need to replicate them -- that'd be a waste of die space.

 

[Carl B]

Going back to the subject of the NV47 and the NV48, and their relation to the G70 and G80, I've heard and read several things about the NV48 that would seem to indicate the chip is nothing more than a NV45 ready to address 512 MB's of RAM - so in essence, not a new core at all.

Who knows, that might not be the case, but I believe since they demonstrated their 512 MB prototype recently, it should be fairly easy to determine whether that was their purported NV48 or not.

 

[WaltC]

I was under the impression that you can't compare ATI transistor counts and NVidia transistor counts - they each "count differently".

I was also under the impression that because they "count differently" (presumably) the transistor-count numbers bandied about by both companies are equally unreliable and uninformative...

We've at last escaped the era where processor performance was thought to be soley the result of MHz; perhaps it's time that we graduate from the "my transistor count is bigger than yours--if you count them my way" school of thought as being equally uninformative in terms of gpu performance.

This amounts to 39% more transistors in NV40 compared with R420, versus a 2% difference in area - 220 versus 160 million transistors against 287 versus 281 mm squared.

Even assuming this might be factually correct, what solid and undeniable conclusions can be drawn from it?

As to the multi-core thing, well I'll just throw my multi-GPU Xbox 360 theory in for laughs. Hahahaha

Jawed

Ever notice how the newest technopop buzzwords ignite literal fads of naming them with everything?... Myself, I'm going to be picking up my MultiCore PSU this week end, not to mention my MultiCore USB keyboard... Next month it'll be a MultiCore LCD flat panel diagonally measured, zero-pixel deficit monitor with silver multicore bells...!

 

[psurge]

I disagree. I can think of several reasons why you might want to replicate them:

- since a defect in one of these areas might well require scrapping the chip, reduncancy could be used to improve yield
- once you start increasing the number of vertex and pixel pipes, and as triangles get smaller and smaller, at some point clipping, rasterization, and vertex cache access will become a bottleneck.
- you might want to be able to process N pixel and geometry streams simultaneously, coming from the same or different applications.

 

[KimB]

Right, but the current incarnation was obviously designed for greater latencies and discrete boards and such. I was speaking in principle and I should have pointed that out. Neither am I saying that this scaled down version of the current SLI should be then SLIed on a video card scale. But...should you operate closer as a two-core-per-package allows you can get away with some more things that the current implementation cannot. Maybe I am too optimistic in every direction, but I think the current SLI is a planned technology with a future. Not all of the goodies are going to be served immediately. The milking and refining of the technology must be done.

You wouldn't want to do anything like SLI with only one memory bus available anyway. You'd basically want the entire system to think that those two cores are really just one core with more pipelines. That'd be by far the most efficient way of doing things, and it requires a unified I/O interface for the two cores.

In the end, then, you'll end up not only having to deal with the engineering challenge of getting two separate chips to communicate on the same packaging, but you'd have to add a third I/O chip onto the packaging. This opens up a whole new can of worms in terms of engineering difficulties (blending, anyone?), and may in fact be more expensive than what is done today, assuming that it can be done efficiently.

If you use SLI, then you'll have an expensive setup that doesn't reach the performance of just taking the larger, lower-yield chips and using them instead.

Perhaps we should consider the Asus dual 6800 Ultra and Gigabyte's dual 6600GT when thinking about this.

No, because each chip still has its own memory. It'd be really inefficient to split the memory bus between the two chips, both in memory space utilization and in bandwidth.

 

[DegustatoR]

Going back to the subject of the NV47 and the NV48, and their relation to the G70 and G80, I've heard and read several things about the NV48 that would seem to indicate the chip is nothing more than a NV45 ready to address 512 MB's of RAM - so in essence, not a new core at all.

NV40/45 was always able to address 512MB of RAM.

Who knows, that might not be the case, but I believe since they demonstrated their 512 MB prototype recently, it should be fairly easy to determine whether that was their purported NV48 or not.

I'm pretty sure that NV48 is just an NV40 made at TSMC. Whenever it's 130 or 110 we'll see soon enough.

 

[Mulciber]

I'm pretty sure that NV48 is just an NV40 made at TSMC. Whenever it's 130 or 110 we'll see soon enough.

i disagree, it's never soon enough

 

[Jawed]

This amounts to 39% more transistors in NV40 compared with R420, versus a 2% difference in area - 220 versus 160 million transistors against 287 versus 281 mm squared.

Even assuming this might be factually correct, what solid and undeniable conclusions can be drawn from it?

These figures are from B3D's 3D Tables:

http://www.beyond3d.com/misc/chipcomp/

There's little doubt in my mind that the Die Size measurement is very wobbly, because Dave used a wobbly old-school ruler. I suspect that the outer dimensions aren't an accurate determinant of the die size, either...

What conclusions can we draw? That we're being bullshitted.

Jawed

 

[Xmas]

You wouldn't want to do anything like SLI with only one memory bus available anyway. You'd basically want the entire system to think that those two cores are really just one core with more pipelines. That'd be by far the most efficient way of doing things, and it requires a unified I/O interface for the two cores.

In the end, then, you'll end up not only having to deal with the engineering challenge of getting two separate chips to communicate on the same packaging, but you'd have to add a third I/O chip onto the packaging. This opens up a whole new can of worms in terms of engineering difficulties (blending, anyone?), and may in fact be more expensive than what is done today, assuming that it can be done efficiently.

If you can attach two chips to each other, why not a third? Another possibility is to design a master/slave setup with different dies.
Blending would be part of the I/O chip, just as it can be considered part of the memory controller on today's chips.

There's little doubt in my mind that the Die Size measurement is very wobbly, because Dave used a wobbly old-school ruler. I suspect that the outer dimensions aren't an accurate determinant of the die size, either...

Outer dimensions? You mean, as opposed to actually used, functional die area?

 

[Geo]

Orton stated 10-15% initially, and I'm fairly comfortable there was no old-school ruler involved.

http://www.beyond3d.com/interviews/daveorton/index.php?p=3

Given the tranny counts, this is no doubt where the head-scratching commenced, and trial-balloon floaters for an explanation. I suspect they eventually figured out a real answer, but whether it will ever be shared publicly is an entirely different question.

 

[Jawed]

Another quote from that page:

"We focused on performance, schedule, features and cost. Our trade-off was that we wanted to maintain our performance leadership and hit a die size that we felt could be produced in volume. ATI is very confident that we picked the best path for the enthusiast market in 2004."

Jawed