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Finally, the design and implementation of the EIB has a curious side effect in that it limits the current version of the CELL processor to expand only along the horizontal axis. Thus, the EIB enables the CELL processor to be highly configurable and SPE’s can be quickly and easily added or removed along the horizontal axis, and the maximum number of SPE’s that can be added is set by the maximum width of the chip allowable by the reticule size of the fabrication equipment.
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The first application of Cell processors is supposed to be in Workstations. The ISSCC showing and IBM's first prototype is no guarentee of what will be in any system - it's a reconfigurable chip. It could be this 1:8 system is hard to manufacture and IBM used it as a show of strength, where in reality the failure rate means a 1:4 Cell is all that's viable at the moment for mass production and might be what appears in PS3.
The first application of Cell processors is supposed to be in Workstations. The ISSCC showing and IBM's first prototype is no guarentee of what will be in any system - it's a reconfigurable chip. It could be this 1:8 system is hard to manufacture and IBM used it as a show of strength, where in reality the failure rate means a 1:4 Cell is all that's viable at the moment for mass production and might be what appears in PS3.
for workstation??? with poor double precision float(30Gflops)?
if ibm use 4 SPE with fully DP ,performance about 128 Gflops(DP), and chips size smaller
for workstation??? with poor double precision float(30Gflops)?
if ibm use 4 SPE with fully DP ,performance about 128 Gflops(DP), and chips size smaller