eight SPU cell chip for PS3?

Jaws said:
version said:
EIB bus use 4 ring , (2 forward, 2 back)
if use 6 SPE then 2-1 ? :D

4,8 possible, bigger not , latenci too much

Not sure, why isn't a 1:2 possible?

because if 6 SPE then EIB has 1 back-ring, 2 forward-ring, and this isnot balanced system
 
version said:
Jaws said:
version said:
EIB bus use 4 ring , (2 forward, 2 back)
if use 6 SPE then 2-1 ? :D

4,8 possible, bigger not , latenci too much

Not sure, why isn't a 1:2 possible?

because if 6 SPE then EIB has 1 back-ring, 2 forward-ring, and this isnot balanced system

cell-9.gif


http://www.realworldtech.com/page.cfm?ArticleID=RWT021005084318

RWT said:
...
Finally, the design and implementation of the EIB has a curious side effect in that it limits the current version of the CELL processor to expand only along the horizontal axis. Thus, the EIB enables the CELL processor to be highly configurable and SPE’s can be quickly and easily added or removed along the horizontal axis, and the maximum number of SPE’s that can be added is set by the maximum width of the chip allowable by the reticule size of the fabrication equipment.
...

It sound like you can add SPE's horizontally in the above config. to have 6 SPE's, no?
 
ZoinKs! said:
version said:
why made ibm a cell with 8 spe if sony not use it ? impossible
IBM has plans for Cell that has nothing to do with Sony and the PS3.
The first application of Cell processors is supposed to be in Workstations. The ISSCC showing and IBM's first prototype is no guarentee of what will be in any system - it's a reconfigurable chip. It could be this 1:8 system is hard to manufacture and IBM used it as a show of strength, where in reality the failure rate means a 1:4 Cell is all that's viable at the moment for mass production and might be what appears in PS3.
 
Shifty Geezer said:
ZoinKs! said:
version said:
why made ibm a cell with 8 spe if sony not use it ? impossible
IBM has plans for Cell that has nothing to do with Sony and the PS3.
The first application of Cell processors is supposed to be in Workstations. The ISSCC showing and IBM's first prototype is no guarentee of what will be in any system - it's a reconfigurable chip. It could be this 1:8 system is hard to manufacture and IBM used it as a show of strength, where in reality the failure rate means a 1:4 Cell is all that's viable at the moment for mass production and might be what appears in PS3.


for workstation??? with poor double precision float(30Gflops)?
if ibm use 4 SPE with fully DP ,performance about 128 Gflops(DP), and chips size smaller
 
version said:
for workstation??? with poor double precision float(30Gflops)?
if ibm use 4 SPE with fully DP ,performance about 128 Gflops(DP), and chips size smaller

POOR DP performance is arguable, but it's obvious that workstations will have bigger, better, more expensive chips in them. Oh, and more of them too.
 
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