Direct3D feature levels discussion

Discussion in 'Rendering Technology and APIs' started by DmitryKo, Feb 20, 2015.

  1. donjulio

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    Here we go, but Ryan already did the same:

     
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  2. Malo

    Malo YakTribe.games
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    @Ryan Smith is not running 1709 latest Windows and thus doesn't have shader model 6_1, but @donjulio output shows 6_1 as expected.
     
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  3. donjulio

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    You are welcome ;)
     
  4. huebie

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    Can anybody explain what D3D12_VIEW_INSTANCING_TIER_1 is and why it is 1 in dev mode and 0 in normal mode? :D

    @donjulio: Welcome to the underground of the 'nerd graphics elite'. :)
     
  5. DmitryKo

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    You have to read the developer documentaiton for now.

    https://github.com/Microsoft/DirectXShaderCompiler/wiki/Shader-Model-6.1
    https://github.com/Microsoft/DirectXShaderCompiler/wiki/SV_ViewID

    https://msdn.microsoft.com/en-us/library/windows/desktop/mt844813(v=vs.85).aspx
    https://msdn.microsoft.com/en-us/library/windows/desktop/mt844812(v=vs.85).aspx
    https://msdn.microsoft.com/en-us/library/windows/desktop/mt844811(v=vs.85).aspx
    https://msdn.microsoft.com/en-us/library/windows/desktop/mt844816(v=vs.85).aspx

    Shader Model 6 is based on the new LLVM shader compiler framework and SPIR-V bytecode, and new features are introduced gradually with new OS/Driver builds. SM6 has been released to 'normal' mode starting with Windows 1709, but SM6_1 and view instancing etc. are only available when the developer explicitly enables experimental features on the Direct3D12 device with a call to D3D12EnableExperimentalFeatures(), in addition to enabling the developer mode in Windows settings.

    https://github.com/Microsoft/DirectXShaderCompiler/
    https://msdn.microsoft.com/en-us/library/windows/desktop/mt492553(v=vs.85).aspx
     
    #885 DmitryKo, Dec 19, 2017
    Last edited: Dec 20, 2017
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  6. huebie

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    Already read this article but don't know the practical usecase. :D That's what i was up to.
     
  7. DmitryKo

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    https://github.com/Microsoft/DirectXShaderCompiler/wiki/SV_ViewID
    In D3D12, most resources are organized into descriptor heaps (termed 'views' as in D3D11) - this includes Shader Resource View (SRV), Constant Buffer Views (CBV), Unordered Access View (UAV), and Samplers; descriptors for graphics pipeline states like Render Target View (RTV) , Depth Stencil View (DSV), Vertex Buffers, Index Buffers, Stream Output Buffers are directly bound to command lists.

    RT view instancing allows you to re-use ('instance') these resources to draw into several (currently up to 4) render targets in the same draw call, instead of having to make several draw calls.

    This is similar to, but fully independent of, D3D12 draw call instancing where existing graphics command list for an onject is instanced - i.e., is used multiple times to draw several copies of the same object with a single draw call.

    It would for example allow you to perform stereoscopic (left-right eye) rendering using the same regular code path - something that I have been anticipating for the last 10 or so years.

    On current Tier1/Tier2 hardware, view instancing is only possible with draw call looping, which would process every view and all submitted resources.

    On view instancing Tier 3 hardware, the scheduler will be able to eliminate redundant processing for non-instanced resources across the entire pipeline.

    [Edit] clarifications
     
    #887 DmitryKo, Dec 20, 2017
    Last edited: Dec 21, 2017
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  8. huebie

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    So a loop of two view ports (where does it loop?) for VR would take twice the time of one (2D screen), but less time compared to "old methods" (e.g. sending the same draw call again). For my understanding it primarily lowers CPU-Usage; am i right?
     
  9. DmitryKo

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    AFAIK the draw-call loop is implemented by the driver/runtime when shaders or draw commands contain a reference to a view instance.

    I'd guess view instancing gives you control over which vertexes/effects are sent to each render target - so for VR stereo you can skip distant/background objects, skybox, HUD, user interface etc. and render them in mono, while with current brute-force approach you can only render the entire scene twice again.
     
    #889 DmitryKo, Dec 20, 2017
    Last edited: Dec 20, 2017
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  10. huebie

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    Thanks for the explanation. So it is a common usecase in various game-titles where devs can gain performance improvements too. Tier 1 sounds morelike a software feature rather a hardware feature.
     
  11. DmitryKo

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    I've made a small update to my console tool to report new features in Windows 10 RS4 Insider Preview (build 17083) - D3D12_FEATURE_D3D12_OPTIONS4, D3D12_FEATURE_SERIALIZATION, D3D12_FEATURE_CROSS_NODE, and Shader Model 6_2, as well as new tiers for Tiled Resources (Tier 4) and Cross Node Adapter Sharing (Tier 3).

    Here's how the new options are reported in WARP12 (Microsoft Basic Render Driver):
    Code:
    Adapter Node 0:     TileBasedRenderer: 0, UMA: 1, CacheCoherentUMA: 1, IsolatedMMU: 0, HeapSerializationTier: 10
    ReservedBufferPlacementSupported : 1
    SharedResourceCompatibilityTier :  D3D12_SHARED_RESOURCE_COMPATIBILITY_TIER_1 (1)
    Native16BitShaderOpsSupported : 0
    AtomicShaderInstructions : 0
    
    The tool will also report processor architecture of the Windows OS (ARM, ARM64, x86, x64).

    BTW there are also a few peculiar processor architectures defined in the SDK, such as IA32_ON_WIN64 (IA32EL?), ARM32_ON_WIN64 (Windows Mobile Emulator?), IA32_ON_ARM64 (CHPE x86 emulator?), but they are not documented.
     
    #891 DmitryKo, Jan 30, 2018
    Last edited: Feb 14, 2018 at 8:23 PM
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  12. Pinstripe

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    Interesting. What exactly is Tiled Resources Tier 4 and is it supported with current hardware?
     
  13. DmitryKo

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    I'd guess all updates to tiled resources (i.e. virtual memory) functionality require additional TLBs/caches/registers, so Tier 4 support on current hardware is not likely.


    I'm rather interested in the new Cross-Node Adapter Sharing tier - does it correlate with features of multi-die MCM-GPUs, rumored to be employed in next-gen high-end video cards?
    https://wccftech.com/nvidia-future-gpu-mcm-package/
    http://research.nvidia.com/publication/2017-06_MCM-GPU:-Multi-Chip-Module-GPUs
    https://wccftech.com/amd-navi-gpu-launching-siggraph-2018-monolithic-mcm-die-yields-explored/
     
    #893 DmitryKo, Jan 31, 2018
    Last edited: Feb 1, 2018
  14. CarstenS

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    GF390.77 updated ViewInstancingTier from 1 to 2 (same for Volta)

    RSAE 18.2.2 did not much:
    The official launch driver for Raven Ridge does this:
    Additionally, Graphics preemption for Vega 8/Vega 11 regresses back from Primitive to DMA Buffer.
     
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