OMG Acert, that paragraph complete with bolded letters is like maximum eye roll! 
nAo's architectural/instructions improvement list aside, my own entry into the mix in this thread would be a pure 'mild' evolution. On 32nm HKMG as I proposed, I'd say 2 Cells essentially on a single die - with the PPE cores evolved to more robust/functional entities, and the SPEs being of the PowerXCell variety by default (minimum logic increase vs the originals to begin with). Assuming density and thermal gains come in line with the hopes for the new process, I'm pegging this 'Cell Evo' chip at ~150mm^2 with thermals at roughly the present 45nm SOI Cell's... maybe hopefully even below. Clockspeeds I'll leave at 3.2 GHz in consideration of the beefier PPE replacements, memory controller of course updated... and here I think we have a decent chip to serve as CPU in a console. Yes, in this vision the CPU and GPU remain separate once again, but with the additional SPE power I do envision a smart design having a GPU more specifically tailored to the environment.
Now... so with this ~150mm^2 Cell Evo (2Power, 16 SPE), for IBM's HPC purposes I see where the new PPE replacement cores are sufficiently up to the task where blades like the QS series no longer require outboard Opterons, for instance, to coordinate workloads. IBM is freed to pursue more 'pure' Cell-based design options, the unification of the SP and DP Cell variants ensures that all Cells are commodity Cells in terms of internal costs, and to make up for the focus on small die size and low thermals, IBM can of course go for glued-die chips, or just straight up MCMs to compete with more monolithic competitors. The great scaling should favor a many-chip environment for Cell quite well in HPC, so I don't view it as having to compete with 500mm^2 chips to offer benefits in certain environments.
nAo's architectural/instructions improvement list aside, my own entry into the mix in this thread would be a pure 'mild' evolution. On 32nm HKMG as I proposed, I'd say 2 Cells essentially on a single die - with the PPE cores evolved to more robust/functional entities, and the SPEs being of the PowerXCell variety by default (minimum logic increase vs the originals to begin with). Assuming density and thermal gains come in line with the hopes for the new process, I'm pegging this 'Cell Evo' chip at ~150mm^2 with thermals at roughly the present 45nm SOI Cell's... maybe hopefully even below. Clockspeeds I'll leave at 3.2 GHz in consideration of the beefier PPE replacements, memory controller of course updated... and here I think we have a decent chip to serve as CPU in a console. Yes, in this vision the CPU and GPU remain separate once again, but with the additional SPE power I do envision a smart design having a GPU more specifically tailored to the environment.
Now... so with this ~150mm^2 Cell Evo (2Power, 16 SPE), for IBM's HPC purposes I see where the new PPE replacement cores are sufficiently up to the task where blades like the QS series no longer require outboard Opterons, for instance, to coordinate workloads. IBM is freed to pursue more 'pure' Cell-based design options, the unification of the SP and DP Cell variants ensures that all Cells are commodity Cells in terms of internal costs, and to make up for the focus on small die size and low thermals, IBM can of course go for glued-die chips, or just straight up MCMs to compete with more monolithic competitors. The great scaling should favor a many-chip environment for Cell quite well in HPC, so I don't view it as having to compete with 500mm^2 chips to offer benefits in certain environments.
