Design your own Cell

S

semitope

Banned
What would you put in a future Cell processor that would make it your dream processor? With my limited knowledge I am going with a single PPE core clocked at 4ghz or higher and 64SPEs at 5ghz. (yes i have no idea if that is possible :p)

I can't get too technical on memory design, included instructions and feature support etc but will be looking forward to the combinations the more experienced folks come up with and what kind of performance they expect it to have. How would that processor compare to other processors in 1-5 years and how feasible your design is, if its not completely just your fantasy. :LOL:

If you don't like the cell, this is not for you...
 
Fifteen PPEs at 10 GHz and 128 SPEs. :p

Sorry this was a bit of a threadcrap.

semitope said:
You can make your contribution as technical as you wish or as r.....ed as vazels post. A thread can only get as far as the contributors let it. I could have put this in the technical forums but those guys barely know how to have fun not to mention my own "design" isnt quite so technically described. I also wanted to leave room for a little exaggeration for the dreamers. Ignore the exercise if your tolerance is irreparably broken like vazels please.
Click to expand...
Sorry, once I read 64 SPEs at 5GHz I thought we had entered lala land.
 
Last edited by a moderator:
Well, if you wanted to make this a serious thread you would give a total area budget and the space a PPE and SPE consume ...
 
Toss in available/anticipated process nodes as well as thermal and power envelopes as well.
 
Joshua Luna said:
Well, if you wanted to make this a serious thread you would give a total area budget and the space a PPE and SPE consume ...
Click to expand...

archie4oz said:
Toss in available/anticipated process nodes as well as thermal and power envelopes as well.
Click to expand...

Good ideas, numbers for anticipated processes can extrapolated from here:

45nm-cell-2.gif


45nm-cell-1.gif
 
Well a spin off thread about what Cell could have been may have be more interesting.
Any way I feel like to many people think that scle the Cell would be trivial. Some rumours reports that Intel encounter/encountered some problems with its larrabee ring bus. One larrabee core could be twice as big as a SPU, so even in tinier package (not a +500mm² chip) that would be quiet some SPUs for the bus to handle.
 
Nobody knows if the 32 SPEs would have been on a single EIB ring. They could have even been planning to replace the ring with a crossbar. They could have maybe retained the SPEs in blocks of 8 functioning as a unit each with its own PPE, with another bus connecting the four units. Nobody knows.
 
You can make your contribution as technical as you wish or as r.....ed as vazels post. A thread can only get as far as the contributors let it. I could have put this in the technical forums but those guys barely know how to have fun not to mention my own "design" isnt quite so technically described. I also wanted to leave room for a little exaggeration for the dreamers. Ignore the exercise if your tolerance is irreparably broken like vazels please.
 
16 SPEs with 512KB localstore and scatter/gatter instructions transparently using main RAM and LS (makes it possible to effectively use the LS as cache). The bigger LS would need more latency, but old code could still run as fast or faster with a modest increase in clockspeed. Hmm... maybe even 8 "dual SPUs" which dynamically partition 1MB LS between them would make sense.
EIB replaced with a crossbar.
And if BW-Compatibility is no concern: 4-8 MIPS cores instead of the PPE.

further down the road: GPU elements dangling on the internal bus as well, for the PS4 this will allow dropping (most of) the external IO Block on Cell and GPU when both can fit on one die.
 
Without constraints, the whole exercise is pointless. A single 100 GHz PPE with 16 MB of 6-clocks L1 cache would be perfect.
 
assen said:
Without constraints, the whole exercise is pointless. A single 100 GHz PPE with 16 MB of 6-clocks L1 cache would be perfect.
Click to expand...

Yes it is pointless if you have lost your grasp on reality...:rolleyes: There is a portion of the first post which mentions feasiblity though.
 
MIPS looks very power efficient, but there haven't been MIPS CPU designed for speed for a while. the one for PS2/PSP was the last one I believe.
Except the CPU from mainland China (Loongson 2 series), stil meant for servers, nettops and netbooks, but pretty serious (64bit, out-of-order)

I'm awaiting the Loongson 3 CPU, a 10W quad core, with facilitated software emulation of x86. that would be a great server CPU.
not sure if that's meaningful to integrate in a Cell :p
 
mmendez said:
Any particular reason why you would go with MIPS instead of PowerPC?
Click to expand...
Probably personal preference first and foremost, I dont consider PowerPC a very lean design, holding back the Cell to be applied in lower power devices.
MIPS on the other hand should have alot potential , there are synthesizable out-of-order cores available reaching >1 GHz at less than 0.7W (74K Series). I`d love to see what would possible with custom and aggressively designed MIPS Cores.

Its also probably a bad idea to handle all onchip-communication over a full CPU (like its done in CELL over the PPE). Toshibas SPUR Engine for example just has a small controller, and this should be a better solution as most of the time you are just routing some signals around and dont need to bother a CPU for that.
 
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