The following has some updated information about some of the latest instructions added with the microcode updates. https://arstechnica.com/gadgets/201...e-and-meltdown-patches-will-hurt-performance/ Zen's indirect branch predictor apparently does not alias addresses when selecting targets, which is one area where it differs from the more readily reverse-engineered Haswell predictor. Abusing a branch to shift history requires using the target's branch address, rather than one that merely aliases to a subset. Using the whole address seems like it's more expensive. I'm curious if there's an influence here from the TLB. This is apparently why Zen is not getting the IBRS mode setting (prior cores will). This mode initiates a barrier at various transitions based on settings. Zen does get the IBPB instruction and STIBP. The former being some kind of barrier that will block branch history prior to it from affecting what follows, and the latter a setting that keeps SMT threads from influencing each other's indirect prediction entries. For Intel, the IBPB instruction seems like it wipes the indirect predictor, among other things. AMD's version was described as a subset somewhere in some patch discussions, but what the superset is and what parts of it are included isn't clear. Elsewhere, I did find that IBM's Power 7 and Power 8 are being updated to handle Meltdown and Spectre. Power 9 has something inbound. Earlier versions are under review. I'm curious about the in-order but very aggressive Power 6. Fujitsu seems to be admitting at least some of these vulnerabilities apply to some SPARC variants, not sure which of them. News articles indicated that Cavium admitted that the ARM ThunderX2 (formerly Broadcom's Vulcan core that had its sights set on a Haswell-like target) is affected by Meltdown and Spectre. Not sure about MIPS and the most recent OoO cores.