Central Processing Unit - Twin PowerPC 602 CPUs at 66 MHz. The design initially called for a single 602.
32-bit RISC microarchitecture
PowerPC CPU designed for consumer electronics applications. The only scalar PowerPC
1.2 watts power usage each
32-bit general purpose registers and integer ALUs, 64-bit data bus at 33 MHz
4 KiB data and instruction caches (Level 1). No Level 2 cache
1 integer unit, 1 floating point unit, no branch processing unit, 1 load/store unit
SPECint92 rating of 40 each, approximately 70 MIPS each.
1 million transistors manufactured on a 0.50 micrometre CMOS process
Custom ASICs
BDA:
Memory control, system control, and video/graphic control
Triangle and setup engines, MPEG-1 decoder hardware, DSP for audio and various kinds of DMA control and port access
Random access of frame buffer and z-buffer possible at the same time
CDE:
Power bus connected to BDA and CPU
"bio-bus" used as a low-speed bus for peripheral hardware
Renderer capabilities:
1 million textured triangles/s geometry rate
100 million pixels/s fill rate
shading: flat shading and gouraud shading
texture mapping
decal, modulation blending, tiling (16K/128K texture buffer built-in)
hardware z-buffer (16-bit)
alpha channel (4-bit or 7-bit)
320x240 to 640x480 resolution at 24-bit color
Sound hardware - 16-bit DSP at 66 MHz (within BDA chip)
Media - Quad-speed CD-ROM drive (600 KiB/s)
RAM - Unified memory subsystem with 8 MiBs
64-bit bus resulting in peak 533 MiB/s bandwidth
Average access 400 MiB/s
Full Motion Video - MPEG-1
Writable Storage - Memory cards from 128 KiB to 32 MiB
Expansion Capabilities - 1 PCMCIA port (potentially used for Modems, Ethernet NICs, etc)
