Can SRAM be designed for unified cache/eDRAM functionality (RSX)?

[j^aws]

Just thinking aloud on how PS2's backwards compatibility could be implemented in PS3.

Can 4MB of SRAM be used to simulate 4MB of eDRAM, from PS2's Graphics Synthesizer, when emulating on RSX? And also have dual functionality as 4MB of TurboCache? I guess that would be an awful lot of transistors depending on how many transistors needed per bit?

IIRC, usually 6 trannies per bit for SRAM, 192 mil trannies! There must be some tech out there that can achieve this with fewer trannies?

 

[Shifty Geezer]

IIRC, usually 6 trannies per bit for SRAM, 192 mil trannies! There must be some tech out there that can achieve this with fewer trannies?

1T SRAM? If they want 4Mb SRAM for emulation, why not just go with cheaper eDRAM?

 

[version]

memory hierarcy in rsx:

mem(50 Gb/s)->cache(250 GB/s)->localstore(1TB/s)

 

[tema]

Why SRAM and not EDRAM?

 

[j^aws]

1T SRAM?

Ah yes, IT SRAM, forgot about that tech! Refresh my memory, was it really 1 tranny per bit? And the chances of Sony using it? It would mean far fewer, around 32 mil trannies for 4MB...

If they want 4Mb SRAM for emulation, why not just go with cheaper eDRAM?

Because cheaper eDRAM wouldn't suffice as cache (TurboCache). The 4MB of SRAM that I'm referring to would act as a fully functioning cache block and the 4MB of eDRAM 'simulated' would be a subset, dumb RAM.

mem(50 Gb/s)->cache(250 GB/s)->localstore(1TB/s)

Can you elaborate?

Why SRAM and not EDRAM?

See above reply.

 

[j^aws]

Apparently Sony are a Mosys 1T SRAM licensee?

...
First 1T-SRAM licensees start volume production. New licensees include Conexant, LSI Logic and Sony...

http://www.firsteda.com/products/mosys/
http://www.mosys.com/company.html

 

[Laa-Yosh]

Ah yes, IT SRAM, forgot about that tech! Refresh my memory, was it really 1 tranny per bit?

It's called like that because it's EDRAM actually. Probably some latency stuff there makes them call it SRAM, but it isn't.

And the chances of Sony using it? It would mean far fewer, around 32 mil trannies for 4MB...

Where are they going to manufacture the RSX? I believe that is a clear indication of what tech they might be able to use.

 

[Titanio]

Where are they going to manufacture the RSX? I believe that is a clear indication of what tech they might be able to use.

Sony are manufacturing it, solely I believe. At which specific plant, I'm not sure.

 

[weaksauce]

Sony are manufacturing it, solely I believe. At which specific plant, I'm not sure.

http://www.nvidia.com/object/IO_21111.html

"RSX will be manufactured at Sony Group’s Nagasaki Fab2 as well as OTSS (joint fabrication facility of Toshiba and Sony)."

 

[aaronspink]

Ah yes, IT SRAM, forgot about that tech! Refresh my memory, was it really 1 tranny per bit? And the chances of Sony using it? It would mean far fewer, around 32 mil trannies for 4MB...

1T SRAM is just a marketting term for a specific implementation of eDRAM. 1t "SRAM" certainly isn't static.

Because cheaper eDRAM wouldn't suffice as cache (TurboCache). The 4MB of SRAM that I'm referring to would act as a fully functioning cache block and the 4MB of eDRAM 'simulated' would be a subset, dumb RAM.

Um, the so called "TurboCache" is just normal standard vanilla GDDR in all current implementations.


Aaron Spink
speaking for myself inc.

 

[j^aws]

1T SRAM is just a marketting term for a specific implementation of eDRAM. 1t "SRAM" certainly isn't static.

It did sound to good to be true if they managed to get the equivalent of 1 tranny from 6 trannies. Which then brings me back to my original question of another type of SRAM with fewer trannies per bit...?

http://www.beyond3d.com/previews/nvidia/nv44/index.php?p=2

Um, the so called "TurboCache" is just normal standard vanilla GDDR in all current implementations.

If nVidia describe the GDDR as the 'equivalent' of cache, hence TurboCache, then that's not what I was describing. My description was the L2 cache in the above TurboCache pipeline. The cache would be 4MB SRAM in 'RSX mode' but would also act as 4MB eDRAM in 'PS2 GS mode'... which was my original question and musing if it would be possible...?

 

[overclocked]

I take it as you mean they "could" speed up the RSX portion of PS3 or atleast hold some usefull information in it to "lessen" the bandwith limitations and aswell act as the backwards compability for the the PS2?

Edit

Of course with the "speed" up of the PS3 RSX subsystem as the driving point of such a implemention then correct?

 

[Teasy]

It did sound to good to be true if they managed to get the equivalent of 1 tranny from 6 trannies. Which then brings me back to my original question of another type of SRAM with fewer trannies per bit...?

1T-Sram does have performance very close to actual SRAM, its the closest your going to get to SRAM without using 6 transistors per bit.

BTW, could you stop referring to transistors as trannies please, where I live trannies is a common shortening of the word transvestites

 

[aaronspink]

1T-Sram does have performance very close to actual SRAM, its the closest your going to get to SRAM without using 6 transistors per bit.

No, not really. There is still always 4t and 5t sram designs. edram based designs can fill a middle spot in latency and speed but for ultra-low latency and high speed, sram is still the only way to go.

Aaron Spink
speaking for myself inc.

 

[overclocked]

1T-Sram does have performance very close to actual SRAM, its the closest your going to get to SRAM without using 6 transistors per bit.

BTW, could you stop referring to transistors as trannies please, where I live trannies is a common shortening of the word transvestites

You little Ninty....

 

[Teasy]

No, not really. There is still always 4t and 5t sram designs. edram based designs can fill a middle spot in latency and speed but for ultra-low latency and high speed, sram is still the only way to go

Ok, I'll rephrase to significantly less transistors. Who currently designs 4/5t Sram by the way?

You little Ninty....

I'm a Ninty?

 

[j^aws]

I take it as you mean they "could" speed up the RSX portion of PS3 or atleast hold some usefull information in it to "lessen" the bandwith limitations and aswell act as the backwards compability for the the PS2?

Edit

Of course with the "speed" up of the PS3 RSX subsystem as the driving point of such a implemention then correct?

Yep, pretty much as the solution would kill a few birds with one stone so to speak. Though it would be a very large transistor cost, unless they have something up their sleeves!

BTW, could you stop referring to transistors as trannies please, where I live trannies is a common shortening of the word transvestites

Hmm, explains why northern chicks always have 5 o'clock shadows!

 

[Jawed]

http://www.beyond3d.com/previews/nvidia/nv44/index.php?p=2

My description was the L2 cache in the above TurboCache pipeline. The cache would be 4MB SRAM in 'RSX mode' but would also act as 4MB eDRAM in 'PS2 GS mode'... which was my original question and musing if it would be possible...?

I'm not sure if you're aware that the L2 cache in that diagram is the L2 texture cache. Perhaps 16K, maybe 32K in a big GPU such as RSX.

The MMU is just providing the ROPs and the texture caches of the GPU with a link to system RAM, RAM that lies on the other side of, in this case, the PCI Express bus.

Jawed

 

[j^aws]

I'm not sure if you're aware that the L2 cache in that diagram is the L2 texture cache. Perhaps 16K, maybe 32K in a big GPU such as RSX.

The MMU is just providing the ROPs and the texture caches of the GPU with a link to system RAM, RAM that lies on the other side of, in this case, the PCI Express bus.

Jawed

Yep, I'm fully aware thanks, hence my thread title and it's implications...

 

[Jawed]

OK, but TurboCache actually refers to the architecture integrating memory distant from the GPU (i.e. on the other side of the PCI Express bus in a PC) and making it appear to be part of local memory.

In PS3 the TurboCache memory would be the XDR. It's a complete misnomer (it's not a cache at all, just non-local memory) and I wasn't clear on which bit of cache you were expecting could serve as dual-use, the actual L2-texture cache or "TurboCache".

Jawed