Can PS2 be considered a pure 128 bit machine??

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patroclus02

Newcomer
According to

http://www.segatech.com/technical/cpu/index.html

CPU's are defined by their integer size, and the SH-4 supports 32-bit integer values, so the SH-4 is classified as a 32-bit processor. By the way a 64-bit processor would be overkill for any console, and none exists. That includes Sony's PS2 and Microsoft's X-Box.
Click to expand...

As far as I know, Emotion Engine is a 128 bit CPU. The MIPS core could be a 32 bits CPU, but I think general purpose registers are also 128 bits. Maybe I'm getting confused with the FP registers, and EE MIPS core is a 32 bits CPU??

Also, the N64 CPU, a cutomized R4000, is known to be a 64 bits CPU. So, is these web wrong about these info??
 
the good old times when for hype sake bigger bits where better eventhough it hadnt that much to do with the real overal power.

16 bit in big on the Sega megadrive
32bit in big on the Amiga CD (what was the name again? it was based on the A1200)
N64 .. its in the name
 
patroclus02 said:
According to

http://www.segatech.com/technical/cpu/index.html



As far as I know, Emotion Engine is a 128 bit CPU. The MIPS core could be a 32 bits CPU, but I think general purpose registers are also 128 bits. Maybe I'm getting confused with the FP registers, and EE MIPS core is a 32 bits CPU??

Also, the N64 CPU, a cutomized R4000, is known to be a 64 bits CPU. So, is these web wrong about these info??
Click to expand...
There is no definite difinition of an x-bit machine. Some charateristics are:
1) Registers
bit-width of general-Purpose registers (128 Bit for PS2, 32 Bit for x86, 64 Bit for x86-64)
2) Operations
You can further divide this into two classes:
a)Scalar (biggest single value operation): 64 Bit for PS2 except multiply+divide (32Bit)
b)Vector: Typically 4*32 Bit, 8*16 Bit, 16*8Bit SIMD - 128 Bit (Register-size) for PS2
3) Bus-width
Bus-width. this is 128Bit for PS2, 64Bit for PCs
4) Adressable Memoryspace / 5)supported Physical
those two sometimes differ, for example for Athlon64: 64 Bit adressable, but something like 42-48 physical, means you are limited to 2^48 Bytes physical Memory on current A64s
32/32 for PS2, 32/32 Bit for x86, 64/~48 Bit for x86-64

Dependend on whom you ask you get a different combination of those 5 points as requirement for an x-bit machine. I`d rate the PS2 as 64Bit machine as the CPU can deal natively with 64Bit scalars and has a >=64Bit Bus
 
Npl said:
Scalar (biggest single value operation): 64 Bit for PS2 except multiply+divide (32Bit)
Click to expand...

64 bits? I thought it was 32 bits... so, the scalar ALU in MIPS core handles 2 x 64 bits operands ??
By the way, add+multiply, floating point or integer? As far as I know, MIPS core can work with scalar integers only. An external FP coprocessor is present.

Then, the web page I posted is wrong about PS2 being a 32 bit machine.
I suppose N64 is a 64 bits CPU, but it states that

By the way a 64-bit processor would be overkill for any console, and none exists. That includes Sony's PS2 and Microsoft's X-Box.
Click to expand...

:oops:
 
Last edited by a moderator:
Just to throw oil on the fire, it would also depend on what you wanted to classify as an "arithmetic operation"...

Technically the PS2 *can* manipulate 128-bit integers in a single operation, provided you count logical ops like AND and OR... :)

The most common "definition" I've seen used in the past seemed to be essentially the bus-width of whatever architecture was in question. If we want the C64 to be 8-bit, the early Amiga to be 16-bit, the later Amigas and PS1 era consoles to be 32-bit etc... then this works. And if you follow that, the PS2 was pretty much a 128-bit console.

Personally though, as no-one can seem to agree on a definition, and frankly even with one it'd be a relatively meaningless label, I don't see the point of trying to decided on a definitive answer...
 
sonyps35 said:
The Atari Jaguar was the last true 64 bit machine!
Click to expand...

Not true : the data bus was 64 bit, but the two RISC DSP were 32 bit and the main CPU was just a Motorola 68000.
 
More bits are only useful if you're working in data of that size. A 8 bit processor that reads/writes and processes 8 bit values is great for integer math from -128..127. If you had to perform the same calculations on the same processor but with extended 64 bit maths support, you'd be using 8x the memory for the same results. If you want to work with 32 bit numbers, on an 8 bit processor you have to fiddle your way to spread the number over 4 seperate values, whereas in a 32 bit CPU you can work with the whole 32-bit value, and that means considerable savings.

I'd say the bittage can be summed up adequately as the maximum size of data the ALU's can calculate on. If a processor can work natively with 128 bit data, it'd be a 128 bit processor, even if 99.99% of the time it uses smaller data formats. I would count vector ops as the smaller field values (so 128 bit v4 maths is 32bit) as you're working in 32 bit values, just with larger data fetches of groupe of 4 32bit values.
 
Technically the PS2 *can* manipulate 128-bit integers in a single operation, provided you count logical ops like AND and OR...
Click to expand...

why?

also, why every FMAC unit can do a single mult+add per clock??
It uses two 128 vector inputs. If using 32bit operands, that would mean 2 mult+add per cycle??
Maybe it has something to do with the topic discussed.
 
patroclus02 said:
64 bits? I thought it was 32 bits... so, the scalar ALU in MIPS core handles 2 x 64 bits operands ??
By the way, add+multiply, floating point or integer? As far as I know, MIPS core can work with scalar integers only. An external FP coprocessor is present.

Then, the web page I posted is wrong about PS2 being a 32 bit machine.
I suppose N64 is a 64 bits CPU, but it states that



:oops:
Click to expand...
64 Bit MIPS (as both N64 and the core in EmotionEngine are) have 64 Bit Scalar Integer operations (ALU operations) and optional FPU coprocessor - either 32 or 64 Bit. the EE has 2 of these ALUs which also can work together for 128-Bit Operations (though apart from bit-operations they arent 128-Bit Scalar, but multiple smaller scalars - SIMD ) - or handle 2 seperate 64-bit operations.
add+multiply is typically a floating point operation, havent seen an integer-implementaion yet?
 
patroclus02 said:
why?
Click to expand...

Why what? Sorry, didn't quite understand your question...

also, why every FMAC unit can do a single mult+add per clock??
It uses two 128 vector inputs. If using 32bit operands, that would mean 2 mult+add per cycle??
Maybe it has something to do with the topic discussed.
Click to expand...

Um... I think you're getting a bit confused here. The FMACs are only used for the floating-point ops. On the main core, there are scalar ops only - and can only take 32-bit values. The vector units can do vectorised ops on 4x32 values, but they have 4 FMACs each to cope with that. Conversely the vector units only do scalar integer (and 16-bit integers at that).

So plenty of operations in the chip work on 128-bit operands, but most of them treat these as multiple values of 32-bits or less (floats on the vector units, integers on the main core). So if you want to judge a chip on the width of the values it operates on, it's a little unfair to count vectorised operations. I was partly being facetious by pointing out that there are a few ops that operate on "128-bit values" of some kind... but that's a bit of a cheat.
 
Xbox should be a 256-bit machine then. :)

Bring back the bit-edness wars! I like when I get to tell someone who's all enamored with the bit-wars that the Xbox CPU is a 32-bit processor! They get all confused and disappointed lol.

Just the other day I got to explain that an Athlon64 is an awful lot like a 386! Oh man people just clam up!
 
so, the core has 2 ALUs that operate with 2 32bit operands. And these ALUs can be used together to operate with 2 64 bit operands?? but only for logical operations?
 
Npl said:
add+multiply is typically a floating point operation, havent seen an integer-implementaion yet?
Click to expand...
I think integer MADD is part of Mips standard actually.
At any rate R5900 implements 32bit MADD as well as 4x32bit MADD and 8x16 Horizontal MADD (surprising as it may sound, I actually found a use for this operation in my code :p ).
Irony 101 - SPE integer MADD is 16bit :devilish:

patroclus02 said:
so, the core has 2 ALUs that operate with 2 32bit operands. And these ALUs can be used together to operate with 2 64 bit operands?? but only for logical operations?
Click to expand...
Once again - as others have said - the 2ALUs natively work on 64bit operands.
Together, they can work on 128bit operands through SIMD extensions (but most SIMD operations breakdown the operand data into 2x64,4x32,8x16 or 16x8).

MrWibble said:
Technically the PS2 *can* manipulate 128-bit integers in a single operation, provided you count logical ops like AND and OR...
Click to expand...
Don't forget QuadFunnelShift - you can shift 256bit integers in single operation :p
 
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