Baseless Next Generation Rumors with no Technical Merits [post E3 2019, pre GDC 2020] [XBSX, PS5]

Around the 1:38:00 mark The Don (real dev who was on Crapgamer's podcast) discusses the history of ESRAM and his concern that Scarlett may be dedicating too much die space to Raytracing functionality like XO had so much dedicated to ESRAM. With all these reports that PS5 is stronger he mentions his concern that MS may dedicated more die space to RT/Machine Learning.
Didn't MS say that Scarlett was designed for the cloud? Nvidia leverages its Tensor cores and machine learning to bring about accelerated realtime Raytracing, (I have no crystal ball but) AMD is also likely using something akin to Tensor cores in RDNA2 to bring machine learning accelerated raytracing.

If Scarlett is designed with the cloud in mind, are they designing it to be a very capable machine learning device they can leverage for other cloud computing applications? And could they be sacrificing too much die space and rasterization performance giving PS5 the rasterization/traditional performance crown?

 

There’s a lot to unpack there; so I’m
A bit biased when it comes to ML since I now work in ML and AI.

Firstly, tensor cores aren’t the be all end all for fast processing. it doesn’t solve bandwidth or cache issues, and we see this issue with RTX lines vs the Pascal ones. More bandwidth but less cache and some algorithms will still run better on Pascal because of cache size.

It’s not enough to have tensor cores, some algorithms will be bandwidth bound, others compute etc. So it is not so straight forward to just dump in tensor processing units and call it a day.

That being said; people need to understand that the addition of AI makes for some really crazy stuff. Yes, raw compute will be down, frame rates could be capped as well since neural networks will always roughly run at the same speed, the whole network must completely run to deliver an output. But the purpose of AI and ML is to arrive at conclusions that using standard programming cannot; too many rules; too many states or too many permutations. The best way to look at 'why AI' vs traditional programming; the niche for AI is to solve problems that are computationally too taxing or impossible to code that many scenarios for (too dynamic, or requiring the need for intelligence to break out of a standard ruleset. If the purpose of traditional compute is to reduce the workload as much as possible so that it's computable quickly (and in some manner in which you can keep the code manageable and sustainable), ML AI is about tackling workloads that are not computable or unmanageable.

One could easily make the argument that you can go without AI, and that's fine. But having options to solve problems with 2 completely separate methods should help provide some wins that would normally be restricted by the power of the hardware or solve problems that require constant adaption.

a game studio that embraces AI will have a major lead over other studios as they continue down the journey of ML and AI and having the hardware available to be used for multiple purposes makes it useful to examine its usage in more areas than just graphics denoising.

Considering how long a generation is, Ill take detuned hardware for AI support.

 

With some under the impression that the next generation consoles GPUs will be limited to 40 CUs, because of the limited APU die space that's inclusive of the Zen 2 Ryzen CPU and I/O controllers sizes (keeping under 370 mm sq of die space), then where are the supposed RT logic or cores located within such a package size? If the current CUs in the RX 5700/XT are incapable of RT acceleration (or full RT), then by extension those can't be the CU designs for the next-generation consoles. Meaning, any CUs housing RT acceleration or full on RT would obviously be bigger (more transistors) than the current CU footprint seen in the RX 5700/XT - or simply a bigger GPU which doesn't fit the perceived APU die size within the next-generation of consoles.

Should we be looking at a more monolithic APU design?

Better yet, will the RT capable AMD GPUs (CUs) next year be more in-line with the next-generation of consoles? And if so, wouldn't the CU count naturally increase, or the CUs increasing in density because of the additional logic towards RT?

 

Performance will only increase (to the level people are expecting) with a much bigger die space. Simples said the meerkat.

 

The die space in the GPU space has exploded recently with Nvidia breaking the reticle limit. I suppose it could in consoles. Who knows *alstrong shrug*

I hate that I find myself looking at these next gen spec threads, it's way too early! About a year from now is only when things will start to crystalize. It's like how I try to avoid getting hyped for E3 too early anymore (mostly to good success)

 

A prolapse in memory...

 

This pastebin page has being removed. This was one of our best XB2 leak. How odd !

It has probably expired....

 

Congratulations with reply number of the beast. The devil is in the details...

 

So according to the recent leaks of Gonzalo benchmarks, what kind of multiplier should we use on a RDNA Tflop to equate to Vega Tflop? I used to rely on 1.25x, should it be 1.3-1.4 now?

 

Hard to say when we don't know how much above 20000 it reached

 

Just lie to me!

 

In timespy benchmark 5700xt has 1.5x per/tflop advantage over vega 64, 1.43x over vega 56 and 1.22 over rx580

 

I think the comparison with RX580 should be used because they have the same number of CUs. And 1.25 is also what they announced so we should use that number and not the others. But we can say at least that until now AMD have being rather honest with their numbers about Navi !

So I think that an hypothetical Navi 56 CUs should have a 1.25 Tflops advantage compared to Vega56 (and obviously not 1.43).

 

rx 580 has 36cu's vs 40 in 5700xt, we don't know how will behave 56cu navi, maybe it will be as effective as 40cu's version, also we still belive nextgen consoles can have more than 40 navi cu's ?

 

Yes. 52 active CUs

 

Perfect!, one for each VR screen.

 

Wrong. It's gonna be 72: 36 per chiplet!

As much as I'm only joking around, that sort of setup would be great for the next generation. Two chiplets for the PS5/Scarlet, one underclocked chiplet for the PS4Pro/X1X, one heavily defective chiplet for the PS4/XB1.

Or maybe:

• 40CU Navi chiplets shared between the PS5/Scarlet and PS4Pro/X1X.
• 20CU chiplets shared between the PSVita2/XBortable and PS4/XB1.

A 20 CU Navi would probably make for a pretty groovy (and hefty) portable. There are 10CU Vega laptops out there, so a switch from a 10CU Vega on 16nm to a 20CU Navi on 7nm would give us comparable power consumption if we assume the same clockspeed of 1.3GHz.

That would make for a 3.3TF portable