It would be ridiculously inefficient and costly relative to its poor 9.2 TF performance to design a 36 CU chip running at 2Ghz purely for the sake of BC, it's borderline retarded thinking and a waste of 7nm die shrink oppertunity. It's simply not innovative, forward thinking to maximize performance for a new gen, much less offering the best multiplat experience. I don't think Cerny would fully endorse this design all by himself.
I'm wondering why there are no AMD GPUs with 48-52CUs as people are proposing for next gen?
There are 36/40/56/64CU chips. 64 being GCN.
Big Navi is rumored to be 80CU (4*10WGP), Arden is supposed to be 60CU chip (3*10WGP with 4 deactivated) while Oberon is 40CU chip (2*10WGP with 4 deactivated). There is a pattern here...
How feasable is something like 48/52? Did Sony think, based on every other generation that has passed, that 60CU design is not realistic as they wouldnt be able to clock chip high enough to make sense of so much bigger die? Perhaps termals for Navi were meant to be considerably better in design phase of PS5. Perhaps Sony never thought MS is making mini PC inside your living room, and if they werent going to, even with 56CU GPU, they would not be able to clock it above 1.5GHZ duo to thermals, thus making 9.2TF relatively close and chip considerably smaller.
In a sense what I am trying to say is, if Navi was to have better thermals in design phase (so that expensive die can give you most bang for your buck), Sony perhaps had two choices :
36*2.0GHz and 56*1.5GHz console.
36CU one would be smaller, would get you much more bang for your buck from your silicon and would be easy way to keep perfect hardware BC intact. It would also mean using 256bit bus is perfect fit, and would deliver higher pixel fillrate then bigger chip.
56CU part at these clocks would give them 10.7TF instead of 9.2TF, but would also result in a bigger die, requiring wider bus as well.
Now some would say, why not clock it 200-300MHz further? Well, because back when they designed it, they designed it as a console and these clocks on 56CU part required far too much energy to be feasable in console. If knee for this hypotetical Navi was higher above, then clocking it much lower then necessary is pretty much wasting your silicon.
In any case, I am going by github data provided and thinking out loud why would they go with narrow and fast. It does scale better then wide and slow and it does mean you get more out of your silicon, that is getting more and more expensive. Also, AMD cards have shown that there is clear "hole" between 40 and 60CU cards, and there has not been one to fill that space out. Perhaps its for a reason, and looking at how Navi blocks work, it does make sense that there is none.
Why can't you just throw an arbitrary number of CUs at the problem and have the GPU schedulers handle to workloads?
