ARM Cortex-A15 the successor of ARM Cortex-A9

[Exophase]

3-issue OoOE is probably closer to a Pentium 3 after the cache changes. I seriously doubt they put a 9-way issue back-end in this thing like the K8 has.

K8 is K7 with an internal memory controller (not a relevant advantage here) and 64-bit (explicitly omitted). The 9-way theoretical peak issue is pretty much a fluff spec and has little to do with real world performance. Compare with the Bulldozer design, which is claiming better IPC than the more mature K8 designs.

Pentium 3 and K7, both with full speed on-die L2 cache, performed fairly similarly at close clocks. Obviously Cortex-A15 will clock much higher.

 

[metafor]

K8 is K7 with an internal memory controller (not a relevant advantage here) and 64-bit (explicitly omitted). The 9-way theoretical peak issue is pretty much a fluff spec and has little to do with real world performance. Compare with the Bulldozer design, which is claiming better IPC than the more mature K8 designs.

Pentium 3 and K7, both with full speed on-die L2 cache, performed fairly similarly at close clocks. Obviously Cortex-A15 will clock much higher.

I don't know if you can throw away the 9-issue backend. Certainly that doesn't mean there are cases where it would actually issue 9 operations (3 of them being FP after all) but having generalized issue ports without the need for specific types in each sub-pipe has its advantages.

And while the end result of the P3 and K7 were similar, the P3 had a lot of things going for it that the K7 didn't. A 256-bit, 8-cycle access L2 cache interface vs 64-bit, 11-cycle access on the K7. In just about every way subsystem-wise, the P3 was ahead.

 

[Deleted member 13524]

20nm Cortex A15 taped out:

http://www.cadence.com/cadence/news...ages/pr.aspx?xml=101811_arm&CMP=101811_arm_bb


And yes, I just got my "Thread-Digger" achievement.

 

[Exophase]

In the meantime we've learned that A15 has 8 independent execution ports each with a reservation station instead of a unified scheduler.. making it more similar to K7 than P6 afterall.

 

[Arun]

In the meantime we've learned that A15 has 8 independent execution ports each with a reservation station instead of a unified scheduler.. making it more similar to K7 than P6 afterall.

Indeed, they were more aggressive than most of us thought - it'll be interesting to see how that turns out for them in smartphones. CPU power budgets have increased quite a lot in the last 5 years and this is probably the last 'hurrah' on that front IMO - of course, Krait is a lot more reasonable there, so it'll be interesting to see how much that helps Qualcomm (at least in phones as opposed to tablets). Also if we're talking ARM CPU arch and handheld CPUs in general, I feel compelled to post a link to my comprehensive article from January: http://www.beyond3d.com/content/articles/111

BTW, the 20nm Cortex-A15 thing is actually more interesting than it looks - ARM has done that kind of collaboration in the past, but it was always with a bunch of Cortex-M3 cores or stuff like that, not a Cortex-A. I wonder if this is ARM being more aggressive and figuring that would give more interesting information about the process, or if it's TSMC who's actually somehow ahead of schedule for once - not very realistic, but it'd make for a nice change!