No, but I doubt AMD wants to ruin the good image they got with AM4 yet so I'd expect minimum of 3 gensDo we know how many generations AM5 may last? I was going to go Raptor Lake, but it's EOL for the platform.
A significant improvement for sure.
Yes fellas, it's ~30% 1t uplift gen over gen.
Only 2x of what they've said during their FAD.
:^)
Considering the disjoint cluster fuck that is the feature set of AVX-512 ( F, CD, ER, PF, VL, DQ, BW, IFMA, VBMI, 4VNNIW, 4FMAPS, VPOPCNTDQ, VNNI, VBMI2, BITALG, VP2INTERSECT, GFNI, VPCLMULQDQ, VAES) in six different micro architectures (Knights Landing, Skylake X, Cannon Lake, Knights Mill, Ice Lake and Tiger Lake) I think AMD opted for the lowest feature set that is actually used and is the most feasible to implement.And managed to do it with decent IPC gain, even adding AVX512 (double pumped AVX256 per Papermaster, always seemed like the more obvious route vs Intels dedicated hardware)
AVX-512 is a massive advantage in some emulators as well. I hope AMD's implemented version of it works for those.
Zen4 looks like a seriously good CPU. Even though I'd planned to hold on to my 3700x for a good portion of this generation, if not the entire generation, I'm now sorely tempted to upgrade to AM5 with a Zen4.
I will certainly wait to see what Raptor Lake brings though given it should launch only about a month after Zen4 releases. With "only" an 11% average improvement over Alderlake I can see Raptor lake having a chance of taking the crown back again, albeit likely at a much higher power draw (which is ironic give it's heterogenous design).
And then I'll likely want to wait for the 3D cache based 7800x too in the hopes that can leapfrog Raptor Lake in gaming performance again.
Cool, I watched it on a phone so couldn't see the individual details of the comparisons they showed. That's great news.I think AMD showing 32% IPC improvement at 4GHz vs Ryzen 5000 in Dolphin might point in that direction
I missed doubling L2 from 512K to 1MB/core.And managed to do it with decent IPC gain, even adding AVX512
Oh you don't know the whole story about the clock gains.When they showed that 5.5Ghz preview I was assuming they'd stuck with 512K to make those kinds of clock gains
Oh you don't know the whole story about the clock gains.
It's hilarious.
But Z4c is arguably even more hilarious.
Zen4 implements at least: AVX-512F, VL, BW, CD, IFMA, DQ, VPOPCNTDQ, BITALG, VNNI, VBMI, VBMI2, BF16Considering the disjoint cluster fuck that is the feature set of AVX-512 ( F, CD, ER, PF, VL, DQ, BW, IFMA, VBMI, 4VNNIW, 4FMAPS, VPOPCNTDQ, VNNI, VBMI2, BITALG, VP2INTERSECT, GFNI, VPCLMULQDQ, VAES) in six different micro architectures (Knights Landing, Skylake X, Cannon Lake, Knights Mill, Ice Lake and Tiger Lake) I think AMD opted for the lowest feature set that is actually used and is the most feasible to implement.
The opposite actually.Of course, it's possible that are the very complex stuff gets a half-assed microcode implementation.