Transistor performance is a vague term, it could mean frequency, but could mean other things as well.According to TSMC, you either get 35% higher transistor performance at iso power or half the power consumption at iso frequency. 35% frequency improvements implies a 1.6/2.1 GHz base / boost frequency at the same power level. Though, I'd expect AMD to reign in the top boost frequency to lower the high power requirement we see in Vega 64, so around 1.6/1.9GHz for base/boost.
But even if it means frequency, people are looking at this wrong. How much power does Vega 10 consume @ sustained 1.9GHz ? probably close to 500watts or even more. Which means Vega 20 running 1.9GHz will consume about 250w if not more (half the power at iso frequency). Acceptable power consumption, but not earth shattering on 7nm.
Sure it is. Although, when you sand the chip and use a caliper it's ~510mm2. AMD's marketing somehow figured out that they better should not report the full phys die area after Fiji...
We already know it's not a shrink since it has double the memory controllers, which means they've had to create completely new chip layout to begin with. This also means that it's relatively easy to get other changes in.Increasing Vega's frequency to 2.0GHz level will require significant changes to the chip, otherwise the massive increase in power consumption will offset any power efficiency gains from 7nm. The question now is: is Vega 20 a die shrink, or a rework of Vega to accommodate better features. I am leaning toward the die shrink part. AMD wouldn't waste resources on a chip that will soon be replaced by Navi.
What's wrong with HBCC? Works fine for me.I expect a fairly dumb shrink with straight forward fixes and/or removal of broken features (HBCC).
IIRC 1:2 FP64 is also double confirmed.We already know it's not a shrink since it has double the memory controllers, which means they've had to create completely new chip layout to begin with. This also means that it's relatively easy to get other changes in.
At least not until the feature arrives with GFX10. Obviously they exist if there is even a discussion if they will be enabled. Could be a hardware issue with Vega, or a software issue that got put on the back burner. Enabling the feature now won't necessarily garner a lot of sales.A Linux driver dev commented they won't enable the "NGG shaders" until GFX10 aka Navi. Vega 20 is GFX9.06, so no NGG for the Vega.
May be a GF Fab issue with leakage or consistency. That could very well be why 7nm Navi is beating expectations.It's weird because for some reason AMD run their VEGAs at much higher core voltage than needed. The 1200mV at P7 is crazy. My VEGA FE does 1432MHz at only 950mV (or 875mV for mining).
A while back in an EETimes article they also said Infinity allowed them to reroute a chip in a matter of hours. Tacking on a few memory controllers, which as I recall we're the primary use for IF, shouldn't be that difficult in regards to a direct shrink. The FP64 would definitely be different and require a bit of work.We already know it's not a shrink since it has double the memory controllers, which means they've had to create completely new chip layout to begin with. This also means that it's relatively easy to get other changes in.
double confirmed.
I would dare to say that you still want a rectangular die and not too much wasted empty silicon, adding 2 memory controllers would need more work than just adding IF-bus and 2 memory controllers on another side of the chipA while back in an EETimes article they also said Infinity allowed them to reroute a chip in a matter of hours. Tacking on a few memory controllers, which as I recall we're the primary use for IF, shouldn't be that difficult in regards to a direct shrink. The FP64 would definitely be different and require a bit of work.
Not arguing that as PS were the big feature to get the geometry and potentially MCM going. If they had to start from scratch or change direction, it may very well be tied to Navi's development schedule. Or released immediately with limited gain as it may not be fully implemented. Assuming it actually works on Vega and isn't a hardware issue. If that were the case, I'd expect Linux devs to outright remove the code if it was never going to arrive. Those guys hate dead code.No but It can help trusting rtg again. As a Vega owner (mostly due to my freesync display), PS was an interesting feature. And now it's gone. It pretty BS.
Agreed, but in theory a less than optimal design could be created rather quickly. Can't recall what was on the opposite side of the chip, if that's even the case. May just be a longer rectangle.I would dare to say that you still want a rectangular die and not too much wasted empty silicon, adding 2 memory controllers would need more work than just adding IF-bus and 2 memory controllers on another side of the chip
What's wrong with HBCC? Works fine for me.
IWhat about HBCC and Radeon SSG? Does it bring any benefit here?It didn't initially, and the question is if it is needed going forward. DRAM prices are in free fall. I don't know the technical details of HBCC, but a cache controller isn't free in terms of silicon real estate; You need a lot of tags to manage 16GB of cache memory.
1.6GHz and 300W TDP, I guessIf you look at the die size of Vega compared to Fiji, it is clear that a lot was added which wasn't CUs, ROPs and cache memory. What did AMD get out of that ?
1.6GHz and 300W TDP, I guess
Wait what? They've been skyrocketing past couple years and are only slowly towards end of the year and next year expected to start going down (and even then they're not expecting free falling prices)DRAM prices are in free fall.
This might sound far fetched, but I think the high power consumption of VEGA is a consequence of the DRAM supply crunch.
With very high DRAM cost, and HBM2 only adding a premium, AMD could not lower sales prices and make a buck. In order to command a highend sticker price, they had to be somewhat competitive with NVidias offerings. So instead of accepting a 20% lower sales price for a 10-15% less performing part, AMD pushed VEGA chips all the way up the schmoo-plot, with very high power consumption.
The choice of memory also means AMD had very little leeway wrt. binning. AMD could not bin high power consumption dies in a lower performance/priced SKU because the bulk of the cost is in the HBM2 memory subsystem. So they cranked up the core voltage, so all dies could be sold in just two SKUs (not considering the water cooled SKU). There is a lot of spread in power consumption with VEGA boards, as there was with Fury (using a undervolted Fury Nano myself).
Cheers