AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Discussion in 'Architecture and Products' started by ToTTenTranz, Sep 20, 2016.

  1. yuri

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    A Linux driver dev commented they won't enable the "NGG shaders" until GFX10 aka Navi. Vega 20 is GFX9.06, so no NGG for the Vega.

    Btw, Navi won't be here anytime soon. The AMD Q3 confcall didn't hint any early 2019 7nm GPU.
     
  2. DavidGraham

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    Transistor performance is a vague term, it could mean frequency, but could mean other things as well.

    But even if it means frequency, people are looking at this wrong. How much power does Vega 10 consume @ sustained 1.9GHz ? probably close to 500watts or even more. Which means Vega 20 running 1.9GHz will consume about 250w if not more (half the power at iso frequency). Acceptable power consumption, but not earth shattering on 7nm.

    AMD said they designed Vega 10 to operate at max 1.7GHz, They required liquid cooling to come close to 1.6GHz sustained. I expect Vega 20 to be close to 1.7GHz on air, but that's about it. Any higher than that will require a change in the architecture itself.
     
  3. Gubbi

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    250W is still less than air cooled Vega 64. Like I said, I expect AMD to lower peak boost frequency to curb peak power consumption a bit.

    I expect a fairly dumb shrink with straight forward fixes and/or removal of broken features (HBCC).

    Cheers
     
    #5583 Gubbi, Oct 26, 2018
    Last edited: Oct 26, 2018
  4. Pressure

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    It's weird because for some reason AMD run their VEGAs at much higher core voltage than needed. The 1200mV at P7 is crazy. My VEGA FE does 1432MHz at only 950mV (or 875mV for mining).
     
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  5. Despoiler

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    Sure guy. He literally proved what AMD stated, but you are all conspiracy and tin foil hats. Cliff notes on chip manufacturing, it's completely normal. General point. The manufacturer will always be the most accurate source. They have masks. They aren't using calipers and photos to approximate something. It might help you to read the original Reddit thread this information was posted to.
     
  6. yuri

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    *tin foil hat grip intensifies* OK, they didn't use any underfills in pre-Polaris and that's the whole thing, right?
     
  7. Digidi

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    Any Infos?
     
  8. Kaotik

    Kaotik Drunk Member
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    We already know it's not a shrink since it has double the memory controllers, which means they've had to create completely new chip layout to begin with. This also means that it's relatively easy to get other changes in.
     
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  9. ToTTenTranz

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    What's wrong with HBCC? Works fine for me.

    IIRC 1:2 FP64 is also double confirmed.
     
  10. Anarchist4000

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    At least not until the feature arrives with GFX10. Obviously they exist if there is even a discussion if they will be enabled. Could be a hardware issue with Vega, or a software issue that got put on the back burner. Enabling the feature now won't necessarily garner a lot of sales.

    May be a GF Fab issue with leakage or consistency. That could very well be why 7nm Navi is beating expectations.

    A while back in an EETimes article they also said Infinity allowed them to reroute a chip in a matter of hours. Tacking on a few memory controllers, which as I recall we're the primary use for IF, shouldn't be that difficult in regards to a direct shrink. The FP64 would definitely be different and require a bit of work.
     
  11. hoom

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  12. Rootax

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    "Enabling the feature now won't necessarily garner a lot of sales"

    No but It can help trusting rtg again. As a Vega owner (mostly due to my freesync display), PS was an interesting feature. And now it's gone. It pretty BS.
    Reminds me the T&L for the S3 gpu (savage or something like that ?).
     
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  13. Kaotik

    Kaotik Drunk Member
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    I would dare to say that you still want a rectangular die and not too much wasted empty silicon, adding 2 memory controllers would need more work than just adding IF-bus and 2 memory controllers on another side of the chip
     
  14. Anarchist4000

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    Not arguing that as PS were the big feature to get the geometry and potentially MCM going. If they had to start from scratch or change direction, it may very well be tied to Navi's development schedule. Or released immediately with limited gain as it may not be fully implemented. Assuming it actually works on Vega and isn't a hardware issue. If that were the case, I'd expect Linux devs to outright remove the code if it was never going to arrive. Those guys hate dead code.

    Agreed, but in theory a less than optimal design could be created rather quickly. Can't recall what was on the opposite side of the chip, if that's even the case. May just be a longer rectangle.
     
  15. Gubbi

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    It didn't initially, and the question is if it is needed going forward. DRAM prices are in free fall. I don't know the technical details of HBCC, but a cache controller isn't free in terms of silicon real estate; You need a lot of tags to manage 16GB of cache memory. If you look at the die size of Vega compared to Fiji, it is clear that a lot was added which wasn't CUs, ROPs and cache memory. What did AMD get out of that ?

    Cheers
     
  16. yuri

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    IWhat about HBCC and Radeon SSG? Does it bring any benefit here?

    1.6GHz and 300W TDP, I guess
     
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  17. Rootax

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    Didn't they said that Vega has around 40mb of cache ? So i agree, no CU or Rop, but they added a lot of cache. But maybe it was just to compensate some higher latency or something, linked to the higher frequency ? Anyway, the chip is a mess...
     
  18. Gubbi

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    This might sound far fetched, but I think the high power consumption of VEGA is a consequence of the DRAM supply crunch.

    With very high DRAM cost, and HBM2 only adding a premium, AMD could not lower sales prices and make a buck. In order to command a highend sticker price, they had to be somewhat competitive with NVidias offerings. So instead of accepting a 20% lower sales price for a 10-15% less performing part, AMD pushed VEGA chips all the way up the schmoo-plot, with very high power consumption.

    The choice of memory also means AMD had very little leeway wrt. binning. AMD could not bin high power consumption dies in a lower performance/priced SKU because the bulk of the cost is in the HBM2 memory subsystem. So they cranked up the core voltage, so all dies could be sold in just two SKUs (not considering the water cooled SKU). There is a lot of spread in power consumption with VEGA boards, as there was with Fury (using a undervolted Fury Nano myself).

    Cheers
     
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  19. Kaotik

    Kaotik Drunk Member
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    Wait what? They've been skyrocketing past couple years and are only slowly towards end of the year and next year expected to start going down (and even then they're not expecting free falling prices)
    https://press.trendforce.com/press/20181009-3167.html
     
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  20. entity279

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    I think on the contrary, that AMD must have known how expensive HMB is. They may have underestimated to a degree, but I doubt that dictated their binning strategy.

    They've said that they've spent the most design effort into Vega being able to reach higher frequencies. We've speculated that to some extent that the GF process may have let them down.
    So I'd be surprised if they aimed at any one point in the lifecycle for lower frequencies.

    Maybe the high BOM prevented them from enacting a plan B of marketing Vega as an efficient (and definetely further under performing) chip . That's as far as I say this would go
     
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