AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Discussion in 'Architecture and Products' started by ToTTenTranz, Sep 20, 2016.

  1. 3dilettante

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    Is it kind of news that the DSBR is enabled to some extent on many PC games? It doesn't seem like people have noticed, or that there's a clear way to get on/off testing.
     
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  2. Grall

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    So flash attaches to Vega via SATA, rather than PCIe/NVME then. Is SATA interface more area efficient for bandwidth, or maybe cheaper from some other implementation perspective compared to PCIe? Flash controller ASICs might be cheaper, but surely that's mostly because they're lower performance compared to PCIe controllers... You'd need more of them to hit same bandwidth as one x4 M.2-style flash controller.

    Who runs the flash/filing system or whatever passes for one on Vega SSG models (or whatsitscalled)? Is it host CPU, or some onboard processor on the GPU itself, is this kind of info even publically known?

    AMD announced an ARM core integrated into Vega way back in slides, but that was for security stuff IIRC, maybe virtualization. Maybe it double-duties as flash management too. :p
     
  3. 3dilettante

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    I was too hasty in that edit. There looks like there could be IO for flash storage in the blurry shots, but SATA was a mistake on my part. I took another look and it's called NVMe for the product spec.

    It's possible there's an ARM controller for flash storage, or some other controller IP.
    The SOC15 platform includes the PSP, which plays a role in security and initialization for the platform, and that should be an ARM core.
     
  4. Malo

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  5. Rootax

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    AFAIK, no...
     
  6. CSI PC

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    And unfortunately for AMD when some games do promote AMD functionality or specific optimisation they generally sell rather poorly apart from Doom that did stand out as a positive for AMD in terms of perception.
    AoTS and Wolfenstein 2 sales are pretty dire on PC, while games like Forza 7 are rather restricted on sales platforms for PC, or such as Battlefront 2 that has its own debacle around integrated game recurring cost mechanics.
    Also probably does not help the greatest advantage relative to Nvidia in terms of performance/functionality is on Vulkan API for now, and if it does eventually become a popular API by then Nvidia will have enabled more of its own functionality in extensions closing the gap.
     
  7. Megadrive1988

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    Would it be fairly safe to assume that 7nm Vega 20 for HPC / professional market will make use of the new 2.4 Gbps HBM2 'Aquabolt' memory ?
     
  8. ImSpartacus

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    If the controllers can keep up, then yeah.

    Also note that SK Hynix's new Q1'18 databook projects availability of the same 2.4 Gbps 8-hi 1.2V HBM2 in Q1'18, so AMD would have dual sources if they did go for >2.0 Gbps HBM2. That's the best you could hope for since I think only Sammy and Hynix are making HBM en masse.

    [​IMG]
     
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  9. no-X

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    I don't think so. Vega 20 will have 4 HBM channels (Vega 10 has 2), which means that even with current 2Gbps HBM2 resulting bandwidth will be doubled. I think that's more than sufficient.
     
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  10. Anarchist4000

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    Not a question of insertion though as a coherent stream of geometry would choose to bypass culling in the pipeline anyways. It works by removing the need for culling within the pipeline, making primitive shaders useless if they weren't performing some sort of workgroup distribution.

    Missed that then as I thought it was just Raven and Intel's discrete solution with up to 28CUs.

    Does it have extra space though? Further from another heat source sure, but there is far more volume for a heatsink on a CPU than the usual two slot GPU cooler. Even the current liquid GPU coolers don't have that much sink/radiator with air moving. Getting 3x120mm fans on a GPU is borderline absurd. That's why I'm leaning towards a large cooling assembly on an APU outperforming the discrete options. Especially if a case is designed around the cooling. A SFF cooler could be entirely external with significantly lower ambients.

    Thats what I'm suggesting they work around. Replace worst case with current active registers and have them hit at different times. If one wave consumes all the registers the scheduler could suspend execution on the others the same way memory fetches block execution.

    Wouldn't have to affect the 10 wave limit. That's up to 10 waves provided sufficient registers, etc the paging could address. AMD also has wave limits as an API extension more or less doing the same thing.

    Probably a different controller as it's the secure memory processor to work with Ryzen. Bit of a PITA if HBCC is attempting to access encrypted pages all the time. Bigger issue for APUs with a shared pool.

    Vulkan is also Androids API. If Google releases a Switch competitor, producers would want that eventual platform targeted. Not unlike Skyrim being ported years later, but take that step initially as the overlap with PC would be significant.

    All Vegas probably will use it. Even Vega10 could refresh with far more bandwidth. The APUs real funny considering the form factor. Not sure they could use it though, but some SKUs could swap in the faster memory.
     
  11. 3dilettante

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    Tower and slot coolers have different approaches, including the volume of air being driven and if/how it's exhausted out of the enclosure.
    In more mobile or confined form factors, z-height may be more limited than the length or width. A board could opt to give a more generous amount of linear space to a GPU and CPU that aren't a fixed number of mm apart, potentially giving more cross section for air movement with less extensive heat pipes.

    Some of the designs that try to use the case or device skin for part of their thermal management could benefit by giving more surface area to each, though if there are designs that are so focused on the space savings it may be that the discrete option is too large.

    The desire was to put the pipeline and all the long-running waves of a bin on one CU. The current vertex and fragment path for a bin with Vega has more CUs available, and I don't think relaxing register constraints would be sufficient to match the number of wavefronts a bin could launch across multiple CUs in a shader engine. There would also be other resources and flexibility available with up to 16 other CUs in more complex scenarios.
     
  12. CarstenS

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    I would love to see you're right. :)
     
  13. ToTTenTranz

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    AMD cancelling Vega shipments to OEMs and ramping up production for the much more profitable Frontier Edition?



    Considering the OEMs were crapping on the distribution channels for the gaming market, I applaud this decision if true.

    If the chips aren't reaching any gamers anyway and are being sold at a 100% premium, at least sell them in cards that give significantly larger profits. And that's the Frontier Edition for Blockchain Pioneers. Haha...
     
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  14. Rootax

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    Funny thing is the Blockchain driver is crap (except for mining). Even the global windows stability is not very good with them, vram and gpu frequencies are much more limited than with recent drivers (852mhz min for the gpu, go full speed even if slighty loaded, etc). It's a joke. If you sell that as a mining device, at least release new (stable) blockchain drivers...
     
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  15. ToTTenTranz

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    The video says AMD is expected to release more info about this after their investor call, which is later today.
     
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  16. Rootax

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    I watched the video and did not heard a thing about drivers... My bad.
     
  17. eastmen

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    they have to have a ton of defective dies , they should just release them as I've said before with whatever isn't working disabled and sell them as mining cards. Miners will eat them up as long as they get good mhs per watt
     
  18. ToTTenTranz

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    They do?
     
  19. eastmen

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    Sure after all thast why the 56 exists and not just the 64. Even if only 2 dies per wafer don't hit the 56 specs they should still be sitting on hundreds if not thousands of sub 56 dies.
     
  20. ToTTenTranz

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    They will say something about this new "direction" for Vega chips.
    Hopefully, it will include an updated blockchain driver (or blockchain path driver) for the card aimed at "blockchain pioneers".


    Not that miners care much about stability in anything other than mining, though.
    My HTPC with a RX480 mined for almost a month straight, and it only stopped mining when windows forced a reset because of an update.



    But that's assuming the chips have a defect in 2 or more CUs, and not in units that cannot be isolated for full functionality (video blocks, memory controllers, etc.).

    We have no idea how many Vega chips there are with more than 2 non-functional CUs but are still functional in everything else.

    Then there's the question of whether or not it's worth it to pair such chips with HBM2 through an interposer and still be able to sell them with a nice profit.
    Consider that part of the appeal for purchasing a Vega 56 even at $950 is that the card can easily be sold to a gamer for $400 out of gaming prowess alone, in the remote possibility of all the cryptos crashing and no coin is worth being mined.
     
    #5060 ToTTenTranz, Jan 30, 2018
    Last edited: Jan 30, 2018
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