Is it kind of news that the DSBR is enabled to some extent on many PC games? It doesn't seem like people have noticed, or that there's a clear way to get on/off testing.
So flash attaches to Vega via SATA, rather than PCIe/NVME then. Is SATA interface more area efficient for bandwidth, or maybe cheaper from some other implementation perspective compared to PCIe? Flash controller ASICs might be cheaper, but surely that's mostly because they're lower performance compared to PCIe controllers... You'd need more of them to hit same bandwidth as one x4 M.2-style flash controller.We have pictures of Vega, which don't seem to show extra IO (edits: besides some SATA, probably).
I was too hasty in that edit. There looks like there could be IO for flash storage in the blurry shots, but SATA was a mistake on my part. I took another look and it's called NVMe for the product spec.So flash attaches to Vega via SATA, rather than PCIe/NVME then. Is SATA interface more area efficient for bandwidth, or maybe cheaper from some other implementation perspective compared to PCIe?
It's possible there's an ARM controller for flash storage, or some other controller IP.AMD announced an ARM core integrated into Vega way back in slides, but that was for security stuff IIRC, maybe virtualization. Maybe it double-duties as flash management too.
Rapid packed math is functioning in Wolfenstein II now?A slide from the CES techday:
Source:
https://www.forum-3dcenter.org/vbulletin/showthread.php?p=11612392#post11612392
Rapid packed math is functioning in Wolfenstein II now?
And unfortunately for AMD when some games do promote AMD functionality or specific optimisation they generally sell rather poorly apart from Doom that did stand out as a positive for AMD in terms of perception.Right. Just as many games as supported that 3D sound shit AMD introduced with R9 290 series cards, which is zero for all intents and purposes.
With AMD's miniscule and shrinking marketshare, any feature requiring vega hardware-specific coding is going to be dead on arrival.
Would it be fairly safe to assume that 7nm Vega 20 for HPC / professional market will make use of the new 2.4 Gbps HBM2 'Aquabolt' memory ?
I don't think so. Vega 20 will have 4 HBM channels (Vega 10 has 2), which means that even with current 2Gbps HBM2 resulting bandwidth will be doubled. I think that's more than sufficient.Would it be fairly safe to assume that 7nm Vega 20 for HPC / professional market will make use of the new 2.4 Gbps HBM2 'Aquabolt' memory ?
Not a question of insertion though as a coherent stream of geometry would choose to bypass culling in the pipeline anyways. It works by removing the need for culling within the pipeline, making primitive shaders useless if they weren't performing some sort of workgroup distribution.That would be able to avoid insertion, since that is a different spot than originally stated.
Missed that then as I thought it was just Raven and Intel's discrete solution with up to 28CUs.Radeon Vega Mobile was announced at CES. A discrete Vega with 1 stack of HBM2 and 28 CUs.
It should link to a CPU over PCIe.
Does it have extra space though? Further from another heat source sure, but there is far more volume for a heatsink on a CPU than the usual two slot GPU cooler. Even the current liquid GPU coolers don't have that much sink/radiator with air moving. Getting 3x120mm fans on a GPU is borderline absurd. That's why I'm leaning towards a large cooling assembly on an APU outperforming the discrete options. Especially if a case is designed around the cooling. A SFF cooler could be entirely external with significantly lower ambients.It's somewhat in the same realm, although the discrete could benefit from better cooling given the extra space it has--which is the extra space that makes it less compact than the Intel solution.
Thats what I'm suggesting they work around. Replace worst case with current active registers and have them hit at different times. If one wave consumes all the registers the scheduler could suspend execution on the others the same way memory fetches block execution.I would characterize the situation as being more stark than relaxing scheduling constraints. The shaders' register allocations are defined as worst-case and are a fixed amount. The current sitation isn't that they can be scheduled together with better performance so much as sufficiently large worst-case allocations prevent more than a few from being scheduled at all.
Wouldn't have to affect the 10 wave limit. That's up to 10 waves provided sufficient registers, etc the paging could address. AMD also has wave limits as an API extension more or less doing the same thing.This seems to be assuming an additional change to the architecture, since waves are capped at 10 per SIMD. Relaxing register occupancy only goes so far.
Probably a different controller as it's the secure memory processor to work with Ryzen. Bit of a PITA if HBCC is attempting to access encrypted pages all the time. Bigger issue for APUs with a shared pool.AMD announced an ARM core integrated into Vega way back in slides, but that was for security stuff IIRC, maybe virtualization. Maybe it double-duties as flash management too.
Vulkan is also Androids API. If Google releases a Switch competitor, producers would want that eventual platform targeted. Not unlike Skyrim being ported years later, but take that step initially as the overlap with PC would be significant.Also probably does not help the greatest advantage relative to Nvidia in terms of performance/functionality is on Vulkan API for now, and if it does eventually become a popular API by then Nvidia will have enabled more of its own functionality in extensions closing the gap.
All Vegas probably will use it. Even Vega10 could refresh with far more bandwidth. The APUs real funny considering the form factor. Not sure they could use it though, but some SKUs could swap in the faster memory.Would it be fairly safe to assume that 7nm Vega 20 for HPC / professional market will make use of the new 2.4 Gbps HBM2 'Aquabolt' memory ?
Tower and slot coolers have different approaches, including the volume of air being driven and if/how it's exhausted out of the enclosure.Does it have extra space though? Further from another heat source sure, but there is far more volume for a heatsink on a CPU than the usual two slot GPU cooler.
The desire was to put the pipeline and all the long-running waves of a bin on one CU. The current vertex and fragment path for a bin with Vega has more CUs available, and I don't think relaxing register constraints would be sufficient to match the number of wavefronts a bin could launch across multiple CUs in a shader engine. There would also be other resources and flexibility available with up to 16 other CUs in more complex scenarios.Wouldn't have to affect the 10 wave limit. That's up to 10 waves provided sufficient registers, etc the paging could address. AMD also has wave limits as an API extension more or less doing the same thing.
I would love to see you're right.I don't think so. Vega 20 will have 4 HBM channels (Vega 10 has 2), which means that even with current 2Gbps HBM2 resulting bandwidth will be doubled. I think that's more than sufficient.
Funny thing is the Blockchain driver is crap (except for mining). Even the global windows stability is not very good with them, vram and gpu frequencies are much more limited than with recent drivers (852mhz min for the gpu, go full speed even if slighty loaded, etc). It's a joke. If you sell that as a mining device, at least release new (stable) blockchain drivers...
they have to have a ton of defective dies , they should just release them as I've said before with whatever isn't working disabled and sell them as mining cards. Miners will eat them up as long as they get good mhs per wattAMD cancelling Vega shipments to OEMs and ramping up production for the much more profitable Frontier Edition?
Considering the OEMs were crapping on the distribution channels for the gaming market, I applaud this decision if true.
If the chips aren't reaching any gamers anyway and are being sold at a 100% premium, at least sell them in cards that give significantly larger profits. And that's the Frontier Edition for Blockchain Pioneers. Haha...
they have to have a ton of defective dies
They do?
I watched the video and did not heard a thing about drivers... My bad.
Sure after all thast why the 56 exists and not just the 64. Even if only 2 dies per wafer don't hit the 56 specs they should still be sitting on hundreds if not thousands of sub 56 dies.