AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Bondrewd said:
They had all the time in the world to do a base layer spin.
So no.
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Did they have the money/resources though? Who knows. It could also be that the hardware is functional as designed, but it's a shitty implementation and it's not really doing much of anything compared to the additional power it draws, leading to a near-zero sum game.
 
xEx said:
It's probably just hardware broken.
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Which hardware is responsible for people drawing 1:1 or better parallels with NV without knowing details about either NV approach or DSBR and their edge cases? I mean Vega does support ROV which does need some "draw stream binning". So that part works but the rest is sort of dead?
It's the expectations that were set up.
 
Bondrewd said:
They had all the time in the world to do a base layer spin.
So no.
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It could be a more complicated issue than a silicon fix or correction for errata, if there is some design element or system function that did not meet reality the way AMD expected. Not really knowing how AMD's changed geometry stages or hardware look or changed, it may be that Vega's initial implementation has design points that are logically correct but practically counterproductive.
An extreme form of this would be the hobbled implementation of x87 floating point, which remained effectively hobbled over multiple generations and ISA revisions.

MDolenc said:
Which hardware is responsible for people drawing 1:1 or better parallels with NV without knowing details about either NV approach or DSBR and their edge cases? I mean Vega does support ROV which does need some "draw stream binning". So that part works but the rest is sort of dead?
It's the expectations that were set up.
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Does ROV require DSBR? For what it's worth, the feature was listed as being enabled for DX12 while DSBR was publicly a no-show.
If the POPS-related instructions in the Vega ISA are how ROV is implemented, it may be overlaid on the GDS-based ordered count functionality and messaging instructions, although how exactly the counters are used or the values are consumed is unclear from what I tried to glean from the ISA document.
 
3dilettante said:
Not really knowing how AMD's changed geometry stages or hardware look or changed, it may be that Vega's initial implementation has design points that are logically correct but practically counterproductive.
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I sincerely doubt they would talk (as in admitting it exists) about it if it's so fundamentally broken respin can't fix it.
 
Bondrewd said:
I sincerely doubt they would talk (as in admitting it exists) about it if it's so fundamentally broken respin can't fix it.
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Vega 10 was supposedly taped out and had been privately demoed before the initial feature disclosure, and it has continued to be marketed with the feature in the the Vega whitepaper. The posited scenario has them disclosing features for and then selling something they knew was fundamentally broken silicon. That hardware failure would be baked in for any Vega 10 products in the wild, so I'm not sure how such an action wouldn't be as serious an overreach.
If they thought a respin could fix it, they wouldn't have sold the buggy silicon marketed with it.

To provide another example, AMD Jaguar was marketed with a fully-fledged turbo function when it was introduced as a client product and in the consoles on 28nm TSMC. In the end, the marketed range would not materialize until the design was reimplemented at another foundry significantly later, which is a bigger jump than a respin.

AMD's continuing to go through the motions for the products on sale makes me think there's enough there that functions correctly, or their level of desperation is worse than I've assumed.
 
3dilettante said:
their level of desperation is worse than I've assumed.
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Why would they ever be desperate when anything Zen is printing money?
3dilettante said:
To provide another example, AMD Jaguar was marketed with a fully-fledged turbo function when it was introduced as a client product and in the consoles on 28nm TSMC. In the end, the marketed range would not materialize until the design was reimplemented at another foundry significantly later, which is a bigger jump than a respin.
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TSMC and fucked up (at least in some way) nodes was a synonym before 16FF.
 
Bondrewd said:
Why would they ever be desperate when anything Zen is printing money?
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The implication that AMD is marketing primitive shaders in tandem with Vega 10 products that cannot use the functionality without a respin--meaning existing products are malfunctioning--is that they are actively lying to buyers (and investors). Is there some other motivation?
Even if Zen is printing money, which we'll have to wait some quarters to be sure actually happens in a sustainable fashion, that won't change that the RTG cannot justify a significant failure to demonstrate results with the revenues of a different product division.

TSMC and fucked up (at least in some way) nodes was a synonym before 16FF.
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AMD still marketed a feature that could not be salvaged with a respin, so it serves as a counterexample to the idea that every failure to meet marketing is a respin away from happening.
 
3dilettante said:
AMD still marketed a feature that could not be salvaged with a respin, so it serves as a counterexample to the idea that every failure to meet marketing is a respin away from happening.
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Most such failures are respin, maybe relayout away from happening. Even Fermi was salvaged after missing clock targets by what, 20%?
3dilettante said:
The implication that AMD is marketing primitive shaders in tandem with Vega 10 products that cannot use the functionality without a respin--meaning existing products are malfunctioning--is that they are actively lying to buyers (and investors).
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Yes, that's why it's not happening. They won't market something so crucial being fundamentally broken.
 
Bondrewd said:
Most such failures are respin, maybe relayout away from happening. Even Fermi was salvaged after missing clock targets by what, 20%?
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What features was Fermi missing, and did Fermi's clock speeds not match the specs on the sales lists?

Yes, that's why it's not happening. They won't market something so crucial being fundamentally broken.
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Respins do not propagate to products already sold, which are still actively marketed as being capable of using this tech.
 
Bondrewd said:
That's why I imply it's not broken, hardware-wise.
At all.
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I provided examples of features that were actively marketed whose issues went beyond just the logical correctness of silicon.

Reimplementation, architectural changes, and/or eventual replacement were needed to resolve them. The x87 problems are an example of set of fundamental design missteps that allowed for a functional product with serious utilization deficiencies, whereas the Jaguar issue is ambiguous as to whether there were errata or other issues beyond the logic layer that made turbo inconsistent outside of some limited circumstances.

x87's designers pinned their hopes on software handlers that never came, but that particular realization took some time.
Jaguar's architectural disclosure and subsequent product issues coincided with some relatively late-stage and disruptions whose level of intractability may not have been clear until later.

Complex functionality with unexplored corner cases the designers presumed could be handled, or late disruption that proves more difficult to recover from than expected can cause otherwise valid functionality to fall short of what is needed.
 
3dilettante said:
I provided examples of features that were actively marketed whose issues went beyond just the logical correctness of silicon.
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Yes, but here we have fundamental uArch feature being marketed despite being possibly broken down to hardware level. It's not FP coprocessing or turbo misses, it's something fundamental for Vega to be competetive.
Llano backfired on AMD hard enough already for them not to market something fundamentally broken that will take a few years to fix.
 
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