AMD: Navi Speculation, Rumours and Discussion [2017-2018]

Maybe they failed to reach the scalability goal?
Because it's RTG we're talking about.

Well that or I smell abysmal N7 yield for >100mm^2 anything.

 

Scalability from ultra-low to performance parts?

Maybe it's referring to scaling past the 4 setup engine limit.

 

If Navi is only really coming in 2019, I would not give much thought about these rumours. If they have nothing to counter Ampere/Turing in 2018, it would be majorly foolish for them to be targeting a midrange with only 1080 performance as their top of the line. Granted that was the strategy with Polaris, with P10 going head to head with GP106, but if Navi is only coming in 2019, NVidia should have a top to bottom family by then and easily able to refresh it, leaving Navi back behind again. If this is correct, it is suicidal.

 

Good example of a risk management mileston approach was what Nvidia did with regards to P100 and V100; in essence the P100 was needed to ensure risk management for the goal of Volta within HPC and the multiple supercomputer contracts could be achieved both in terms of obligations to timescales and performance-functionality.
One reason they started with the GP100 and reversed the accepted approach to manufacturing GPU die size/complexity, not the only one though.

Not sure AMD had the resources financially and teamwise to split the Vega functionality-complexity into such product milestones, nor how they could prioritise it between architectures as it is fair to say Vega ideally needed to be earlier.

One of the worst examples of poor product-tech risk management recently was the Zumwalt class destroyers, they threw everything in way too early and together without the usual risk milestone implementation.

 

It's incredible how even relatively well informed forum like Beyond3D is taking first rumors coming from Fuad no less as some sort of gospel. Sure, it could be true, but given Fuads track record over the years it's more likely it's not.

 

Fuads track record isn't as awful as everyone makes it out to be, and when he's confident of a story I tend to give him the benefit of the doubt and it hasn't failed me yet over the years.

I really think Fuads gets a bum rap, the guy is just putting up what he hears/finds out...that doesn't always mean it's accurate but it's always interesting.

 

Credit is where credit is due, they got Naples (read EPYC) details right.
Acktually I don't even know if RTG fucked up something again or they're cautious with N7.
Because Vega20 will end up being fairly small for a HPC chip too.

 

I think the source of the rumor may be a switch to a chiplet GPU design, where they are able to combine multiple GPU chiplets to a larger GPU. For example Navi10 could have 32 CUs and a single channel of HBM memory, and it could potentially be used as 1x GPU (32 CUs) + 1x HBM, 2x GPU (64 CUs) + 2x HBM, 3x GPU (96 CUs) + 3x HBM, and 4x GPU (128 CUs) + 4x HBM, or even as the GPU part of an APU (like the Kaby G), only with a xGMI (or whatever) connection between CPU and GPU. So the peeps from the fabs would only see a small Navi10 GPU at first, and probably wouldn't know anything about the scaleability. Technically this should be doable (although it would be really hard), but from the production cost and yield perspective that would be really great, like it was with Ryzen, Threatripper, and Epyc.

 

Also see these two recently published patents:

• Circuit board with multiple density regions
• Circuit board with bridge chiplets

It seems like they are moving away from the old interposers.

 

Wait a sec...
...I can already hear Bohr screeching from the second one.
It sounds so familiar.

 

Isn't the 2nd somewhat similar to Intel EMIB?

 

YES!
I mean, it's literally EMIB in everything but name.

 

Looks that way, but EMIB was connecting an AMD GPU to HBM which isn't exactly an Intel design either. Will be curious to see if AMD licensed EMIB for wider use or how that plays out.

 

Intel said EMIB is ICF-exclusive though.
This is something different.

 

Intel also makes use of EMIB for their FPGA "chiplets"(Transceivers, HBM2, etc)

Yeah, although that does mean 3rd party companies (that go to ICF to manufacture, which is very little may I add) can use it if wanted.

 

EMIB is a one-sided bridge that does not provide connectivity through the silicon, removing the complexity and cost associated with TSVs.
The patent goes further to state that it goes beyond just the silicon-based EMIB and includes other organic bridge types that also only provide one-sided connectivity.

The two methods appear to be more concerned with either a package that is exposed with regions of different feature pitch, or in the case of the second patent a regular package with voids that can be filled with chiplets made in a manner similar to package substrates with more dense feature pitches.
While not committing itself to a feature size, the examples put this closer to the density of fan-out package technologies like TSMC's InFO, with 10 um lines versus an interposer's .065um lines.

This takes AMD's usage of the term chiplet even further afield, as these are small substrate sections generally built like other package types, with no functionality to them like the other sort of chiplets composed of logic printed on silicon.

 

Has anyone seen this patent: PARALLEL MICROPOLYGON RASTERIZERS ? It's very detailed, even including some sample pseudo code.

 

Rumor

• Successor to Vega, still part of the GCN architecture
• 6th GCN generation (GCN6), and also the last GCN generation
• very early roadmaps speaks about "Scalability" and "Nextgen Memory" (after HBM2)
• however, it must break through the limitations of the GCN architecture
• 7nm process of GlobalFoundries and/or TSMC (last tendencies to TSMC)
• specifications of GlobalFoundries' 14LPP to 7LP: -65% chip area with -60% power consumption
• specification of TSMC's 16FF + to 7FF: -70% chip area with -60% power consumption
• earlier mentioned graphics chips: Navi 10 (high-end) and Navi 11 (midrange)
• according to the latest rumors, Navi starts with a midrange solution at the end of the first quarter of 2019 (hypothetical: "Radeon RX 680")
• this midrange solution should reach the performance level of a GeForce GTX 1170/2070 and relies on GDDR6 memory (AMD works on GDDR6 interfaces)
• speculatively 4096 shader units on 200-250mm² chip area with the 7nm process possible
• speculatively this solution can reach the performance of a Radeon RX Vega 64 (+X%) for the power consumption of a Radeon RX 480 (150W)
• whereabouts of the originally planned Navi high-end solution is currently completely unclear (postponed?, canceled?, multi-chip solution?)

Source: 3DCenter.org via AMD Reddit "

So this could be good. The con is its still GCN but if it can give us vega 64 performance at a 150w it could be a competitive midrange card unlike the current vegas. Hopefully at the 200+ watt range it can open up and compete with nvidia. I hope a true successor comes byt the end of 2019 however

 

Aside from process shrink years, haven't we already had basically one major chip per year since GCN?

• 2012 - 3 - Tahiti, Pitcairn & Cape Verde (28nm debut)
• 2013 - 2 - Hawaii & Bonaire
• 2014 - 1 - Tonga
• 2015 - 1 - Fiji
• 2016 - 2 - Polaris 10 & 11 (14nm debut)
• 2017 - 1 - Vega 10
• 2018 - ? - (Does Vega 20 "count" if it's not in consumer desktop cards?)
• 2019 - 2 - Navi 10 & 11 (7nm debut)

2018 is a weird year since not much will probably happen on the consumer desktop side because AMD is very active elsewhere (Vega M, Vega 20, etc), but otherwise, things hold up.

AMD's "slow" pace actually makes it pretty easy to predict. Just seeing that Polaris 10 & 11 will be 3 years old in 2019 shows that Navi 10 & 11 will probably be straight up replacements for Polaris.

Things might get complicated once AMD overhauls GCN (presumably to make it easier to make MCM-style GPUs), but for now, it's pretty straightforward.