AMD CDNA Discussion Thread

It's like to make doubles a first class citizen, which use 2x VGPRs.
The registers typically hold single-precision (32-bit) floating-point (FP) data, but are also designed for efficiently handling mixed precision. For larger 64-bit (or double precision) FP data, adjacent registers are combined to hold a full wavefront of data.

 

Yea, this would also make sense.

Samples of MI200 already exist. Apparently, these are used in HPE Cray EX class of supercomputers. It's interesting that the samples are already being labeled as "MCM". So is it a doubled MI100 or a CDNA2-based MCM-native chip?

Also the "HPC customized" Zen 3-based CPU - Trento - is being paired with the MI200.

 

Aka Shasta.

This.
There's the proper 2-piece MI200 aka the MCM one and the baby MI200 aka the SCM one.

 

MCM makes a lot of sense for HPC markets.

 

AMD Radeon "Aldebaran" GPU Support Published For Next-Gen CDNA

 

Poor MI100 won't even get to live much.
:sadface: for yesteryear ROCm 4.0 delays.

 

It seems HBM2E is alive - ATOM_DGPU_VRAM_TYPE_HBM2E

Also the patch contains "per-die" mentions which further confirm the Aldebaran being MCM-based.

 

A100 80GB already uses it.

 

AMD Instinct MI200 ‘Aldebaran’ GPU seemingly confirmed to be dual-die

 

Being a layman, would it be safe to assume that the scientific workloads (most likely on an MI chip) makes it a better "testing ground" for MCM before progressing to consumer and graphics oriented GPUs?

 

IMHLO: Nothing is a hard as graphics on a competitively interactive scale.

With basically everything else done in GPU, you can mask or afford some kind of latency or uneven distribution of workloads. Even the much-cited recommender systems only have to satisfy a single measure of latency once in while (in terms of GPU timings), not continously deliver single-digit-ms latency to a single user.

edit: Yeah, that's a big THANK YOU to all hard- and software engineers making those chips so we can enjoy our favourite games on them to the fullest.

 

To my understanding those scientific workloads rarely even care whether there's 1 or more chips doing the calculations, so yes and no - Yes as in, it's easy testing ground for MCM since workloads don't care and No, it's not that useful testing ground because games do care.

 

In a sense that a pure compute workload is a lot easier to put on as many processing nodes as possible than graphics yes. But this isn't really related to graphics much so it's not so much of a "testing ground" from s/w perspective - it is a testing ground for h/w though and possibly a testing ground for h/w approaches which would make MCM suitable for graphics.

 

ROCm 4.1 now features an implementation of the Cooperative Groups API on HIP ...

 

Much more significant development, the support for fully coherent UMA with Aldebaran, planned to be upstreamed right now with new merge cycle.
Coherent UMA is possible only in A+A, for Frontier with Trento CPUs and Aldebaran based Instincts.

https://www.phoronix.com/scan.php?page=news_item&px=AMD-HMM-SVM-Manager-v2

 

Genoa should work fine too.

 

interesting..

https://videocardz.com/newz/amd-con...-instinct-mi200-has-primary-and-secondary-die

 

I'm pretty sure AMDs patents on these MCM-GPUs have been pretty clear there's no iod, but all (both) chips are created equal even though only one is handling the communication with CPU

 

Yeah.

 

Computerbase reports a leak where Aldebaran is coming up as a two die, 2x112 CU GPU with uncertain amount of HBM2e

https://www.computerbase.de/2021-06...fikkarten-bekommen-zwei-gpu-dies-und-224-cus/