AMD Bulldozer Core Patent Diagrams

For a mainstream desktop processor, it is big, though it could still be an improvement after yields mature since AMD's Thuban is bigger still.

BD is ~27% larger than a 6-core Westmere and 45% larger than a 4-core SB.

BD is larger than what is comfortable for a desktop CPU and a low-end Xeon.
It would be between a Westmere EP and the eventual Sandy Bridge EP.
It's much smaller than the EX chips.

BD seems to slot between EP and EX sizewise, and its connectivity and features may put it above EP and below EX.

Performance-wise, I dunno.
 
The L2s make much of a comparison of die size pretty much redundant, since they're so much of the die. Each L2 is about half the area of a module.
 
All these server chips set aside a very large portion of the die to cache.
The key is that BD is bigger than the 4-core low-end SB Xeons and the soon to be replaced Westmere EP, but smaller than SB EP or the EX line.
Commercially, it would be most comfortable in the Xeon price ranges and somewhat acceptable at the enthusiast level, which is where it is going.

Saying BD is big for a desktop chip seems like a broad enough statement to not conflict with the second order effects of differing L2 and L3 density.
 
I wonder what a 6-module BD would look like. I bet it will require much more redesign of the layout than the Thuban die had gone through, from its 4-core predecessor. The biggest challenge, I guess, will be the distributed L3 design and re-wiring all the scattered slices together with the cross-bar mesh.
 
Jawed said:
Maybe someone will justify this point of view with an actual argument :?:
Click to expand...

Intel die sizes for the desktop have traditionally been lower than BD, though it too can use the same or very similar sizes at the extreme edition end of the desktop specture.

SB EP ~360
SB 215 mm2 high-mid desktop (half-size variants for lower SKUs exist)
Westmere EP 248 mm2 (Xeon/extreme edition i7)
Nehalem 263mm2 (planned smaller variants cancelled?)
Penryn 110/220 (MCM)
Conroe 140/280 (MCM)

There is a strong desire to keep die sizes low, even below SB if it weren't for the IGP.
What we see with Nehalem is a point where the MCM approach to mainstream and Xeon stopped and probably where Intel was least comfortable, though it had the upside of kneecapping AMD's server efforts.
Westmere and beyond split mainstream and server designs.

AMD has been less able to support that many product lines, over the same time period, but the advent of Llano and BD show a stronger divergence.

AMD
Bulldozer 315
Llano 228
Thuban 346
Barcelona 286
K8 (opteron/athlon) 220

On the desktop, there nothing that crosses 300mm2.
Depending on the rung, there is pressure to be nearer to 200, and if a chip needs to cover the lower mainstream levels, below 200.
AMD's spent longer periods of time with larger dies on the desktop, and we see their level of success.
 
How about looking at it from the angle that Llano is the largest desktop CPU thus far that has been opted for the desktop market without a workstation/server SKU for the chip?

Sandy Bridge is close in size, but it actually does have some Xeon SKUs for workstations.

edit:

Are we talking about different things?
I'm saying that 315mm2 is big for the desktop.
However the internals are arranged, the resulting size is big.
 
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How much redundancy AMD implements to their designs versus Intel?
If AMD has few % more redundancy build into their chip this would explain on average bigger dies from them compared to Intel. But at the same time putting a lot of redundancy into CPU core design seems to be wasteful because AMD can easily salvage CPU's with bad cores by disabling them and creating lower end SKU's.

Or is this fault of automated tools they now using at AMD?
 
Lynnfield is 296 mm^2, but they did cram a whole PCIe controller on it. Also perhaps noteworthy that those were the lower end, decidedly non-server Nehalems.

Edit: nvm, they were sold as low-end Xeons.
 
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3dilettante said:
How about looking at it from the angle that Llano is the largest desktop CPU thus far that has been opted for the desktop market without a workstation/server SKU for the chip?
Click to expand...
Llano is a test chip (for APU). It's a (franken-) dead end. Trinity replaces it after ~ 1 year, with more space-efficient x86 cores.

edit:

Are we talking about different things?
I'm saying that 315mm2 is big for the desktop.
However the internals are arranged, the resulting size is big.
Click to expand...
My point is that with L2 being such a large part of the die and L2/L3 together being maximally redundant parts of the chip, the defect-related consideration of the cost of a 315mm² chip needs to account for cache area (16MB of "un-core" cache).

In terms of dies-per-wafer costs, the "desktop" chip is effectively a salvage part for the server (+ workstation?) chips. Including, presumably, 6-core and 4-core variants on the desktop. No different from salvage GPUs.

So this isn't a desktop-focused chip. Who the hell is going to buy one, anyway? If it's very good at x264 that's one audience. Otherwise? I dunno, who (consumer) buys a desktop processor for sheer performance these days?
 
Otto Dafe said:
Lynnfield is 296 mm^2, but they did cram a whole PCIe controller on it. Also perhaps noteworthy that those were the lower end, decidedly non-server Nehalems.

Edit: nvm, they were sold as low-end Xeons.
Click to expand...
That is an interesting anomaly, and it does reside at the Nehalem transition.
CPU prices seem to have changed since then, since Lynnfield on the desktop could be found priced nearly twice the rumored top price for Bulldozer if it is an i7-2600k competitor.
One of the purported advantages for Lynnfield was that it was a trailing-edge deployment on 45nm prior to the 32nm rollout. I haven't seen numbers on how important this was.


Jawed said:
My point is that with L2 being such a large part of the die and L2/L3 together being maximally redundant parts of the chip, the defect-related consideration of the cost of a 315mm² chip needs to account for cache area (16MB of "un-core" cache).
Click to expand...
At a glance Westmere EP allocates 1/4 of the die to the L3.
What is the ratio for BD L2+L3? Am I being pessimistic when I eyeball it as 1/3 of the overall die?
I'll do better pixel counting when I find time.

In terms of dies-per-wafer costs, the "desktop" chip is effectively a salvage part for the server (+ workstation?) chips.
Click to expand...
There are fully functional FX chips that will sell for ~$320, if the rumors are correct.
They aren't all salvage parts.

So this isn't a desktop-focused chip. Who the hell is going to buy one, anyway? If it's very good at x264 that's one audience. Otherwise? I dunno, who (consumer) buys a desktop processor for sheer performance these days?
Click to expand...
Gamers and media types may.
The focus question goes to how much silicon AMD is throwing out relative to the return.
Selling a chip the size of a Xeon EP for the price of a i7 2600k is something AMD's manufacturing partner and its accountants need to keep track of.
 
Yep, selling salvage server/workstation CPUs into the desktop market is prolly for the accountants' health.
 
fellix said:
I wonder what a 6-module BD would look like. I bet it will require much more redesign of the layout than the Thuban die had gone through, from its 4-core predecessor. The biggest challenge, I guess, will be the distributed L3 design and re-wiring all the scattered slices together with the cross-bar mesh.
Click to expand...

there is a 5-module follow up actually, which is a bit more puzzling (pentagram? :p )
it's also "ehnanced" though we don't know in which way.
 
56220448.jpg


Looks like each slice of the L3 is commanded separately. In the slides from AMD there's something mentioned about partitioning of the L3 cache. The only way to verify this is with multi-threaded memory streaming benchmarks.

More here:

http://pc.watch.impress.co.jp/docs/column/kaigai/20110830_473823.html
 
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