K8 had three integer schedulers. The way I've seen it described is that each one could issue 1 ALU and 1 AGU per clock.
A more detailed overview.
Dedicated MMX pipes? I guess this means the whole x87 legacy stack is "outsourced" from the main FMAC logic...
Apparently this is a part of the modular concept for Bulldozer, and some future revision could simply drop the good old FPU.
More from Charlie
It's one thread per integer block.
If you only have one thread, one of the blocks is going to be idle.
If you only have one thread, one of the blocks is going to be idle.
Jawed
Legend
TechReport's article looks like the first one actually worth reading:
http://www.techreport.com/articles.x/19514
http://www.techreport.com/articles.x/19514
It's the same data already released, though in a few hours the embargo should lift for sites that were given more detailed slides, and then there's the final presentation that should hopefully be available.
I had assumed those slides had already been released because some of the ones in the story were already shown elsewhere, perhaps there was some reuse.
There's nothing in the story itself that I thought was new, though.
Hopefully there's more to come.
There's nothing in the story itself that I thought was new, though.
Hopefully there's more to come.
There might be a bobcat set yet to come; plus some feedback from people who attended the talks!
Edit:
http://www.brightsideofnews.com/news/2010/8/24/bobcat-amds-answer-to-intel-atom2c-arm-movement.aspx
there's even a nice "die map" of sorts; it looks synthesized rather than hand laid. (Aside: It's a bit surprising that hand crafting layouts is still superior to computer synthesization as far as I know; the software used for this probably uses too coarse a heuristic for optimzing circuit paths as things stand.)
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I feel like I wasted my time with the others.
I suspect it's just synonimous for "Integer-SIMD block" and does not literaly mean MMX. It is almost a requirement, as YMMX operations (be it FP or INT) have to utilize a shared / splitable resource.
If they were smart and the four blocks are literally there and four independent shareable resources (despite the nomenclature: FP-module), you could run full-speed 256bit INT-SIMD in parallel with 256bit FP-SIMD. Doesn't seem very realistic though, too much ohh.
Looks like anand posted all the slides from hotchips:
http://www.anandtech.com/show/3865/amd-bobcat-bulldozer-hot-chips-presentations-online
no news on the actual transcript of the presentation. There's some interesting info about the use of pointers to prevent unncessary data movement in bobcat.
http://www.anandtech.com/show/3865/amd-bobcat-bulldozer-hot-chips-presentations-online
no news on the actual transcript of the presentation. There's some interesting info about the use of pointers to prevent unncessary data movement in bobcat.
Here the slide states, "When only one thread is active, it has access to all shared resources".
Does that mean one single thread can share across all 8 integer pipelines, or do those not count as a 'shared resource'?
Integer pipelines are not shared resource's.
from what i read, in single thread mode the second core can be used to execute a speculative istruction in parallel, so if it predict right it increase the ipc
what? 0_0
Nope, that would be problematic on a number of levels. What the "use all shared resources" means is that a single-thread can have its instructions decoded across the entire decoder width, use both the 128-bit FMACs rather than just one etc.
Then what is your interpretation of this image
http://www.hardocp.com/image.html?i...WR1JzVjJzNE1WUlVUbVpOVmpoNFdESjNkV0Z1UW00PQ==