Silicon on insulator key to AMD 90nm success - analyst
By Tony Smith
Posted: 14/11/2003 at 15:20 GMT
AMD's Silicon-on-Insulator (SOI) technology is going to save the company's migration to a 90nm process from the delays that appear to have plagued Intel's shift to 90nm.
So says American Technology Research (ATR) analyst Rick Whittington, who also reckons we should all go out and buy AMD stock.
Whittington's line is that AMD's 90nm ramp is proving so successful, it should be able to ship 90nm Opterons ahead of schedule. As examples of that success, he cites demonstrations of 90nm Opterons that "did not appear to require extra cooling of any special change in the motherboard design". That, he believes, is a sign of the technologies maturity. So are the yields of 2.2 and 2.4GHz 90nm Opterons running at 45W - well below AMD's specified 70W operation.
This is crucial. Intel's initial 90nm part, 'Prescott', has a thermal target of 90-100W, according to Intel spokesfolks, albeit at a rather higher clock speed than the 90nm Opterons. But while AMD can boost clock frequencies at the cost of power consumption, Intel can't lower Prescott clocks in order to drop the power consumption. In short, AMD has more room to manoeuvre. "Our preliminary calculations indicate that a 3-4GHz clock rate is possible, without exceeding the current 85-90W spec." says Whittington.
Doubly so, since AMD isn't selling its chips on the back of their clock frequency. "We think the blade vendors are going to love 90nm Opteron," says Whittington. Blade makers will like Opteron's integrated North Bridge, too, allowing them to reduce each board's chip count.
The maturity of AMD's 90nm process, says Whittington in a note to customers, will allow it to sample 90nm Opterons this year and begin volume wafer starts sometime during the first half of 2004, rather than the H2 2004 target schedule.
It also means that, AMD is going to get a lot more CPUs off a single 200mm wafer than it can at 130nm. The current Opteron die runs to 193mm2, while the 90nm version is 114mm2, according to an AMD presentation seen by Whittington. So while a 200mm wafer yields around 131 130nm chips, it should yield 235 90nm parts. How many will be working is another matter, but Whittington estimates that the cost per chip to AMD is 30 per cent less at 90nm than 130nm, giving it much more room to play off price against margin, allowing it to drive revenue growth or play on price if Intel pushes it in that direction.
What's made AMD's ramp run seemingly more smoothly than Intel's is its use of SOI. That's the technology that's keeping 90nm transistor leakage current down, allowing AMD to get the core voltage and clock frequencies it wants without driving up heat dissipation.
Getting that balance right appears to be what's hampering Prescott. Intel has apparently had to up the core voltage to cope with the greater leakage in the smaller, 90nm transistors, and that has boosted the part's heat output to 100W - more, some source claim.
Interestingly, the grand master of SOI is arguably IBM, with which AMD is partnering to develop 65nm and 45nm processes on 300mm wafers. AMD's first 300mm fab, the location for which is expected to be announced later this quarter, may well require IBM know-how, something that plays into suggestion that the company will site said 300mm fab in spitting distance of IBM's East Fishkill facility - assuming they don't become one and the same fab.
That AMD sees SOI as the key to future chip development is clear from recent research results - as does IBM.
The upshot is, says Whittington, better chip performance - and better financial performance for AMD. The company will be able to punch out more chips, more cheaply, boosting revenues, and thus income. He forecasts profitability of $1 per share for 2004, $2 per share for 2005 and over $3 per share for 2006, though he admits these predictions are "well above consensus". ®
