It really is about homogeneous vs heterogeneous compute, where ff is one type of "core".
Blazkowicz
Legend
we're already seeing that underclocking on quad core i7 for laptops, and dekstop AMD A8-3800, A6-3600.
it's a good throwback to old times - the turbo button's only purpose was to underclock your PC.
I guess it was indeed news for some contributors to this thread, unless they simply decided to ignore it. Sometimes it's easy to underestimate or even forget facts that don't play nice with a given/preconceived vision.
Except that with a homogeneous architecture, you minimize having to communicate across cores!
BS. Are you going to not spill your working set to L3?
That paper lacks an evaluation of executing wide vectors on less wide execution units (i.e. AVX-1024 on x86). So you can throw its conclusions in the trash bin.
Again, it only considers "a hypothetical heterogeneous processor [consisting] of a small number of large cores for single-thread performance and many small cores for throughput performance." It does not consider achieving high throughput out of unified cores.
Both these papers utterly fail to recognize that workloads do not consist of separate sequential and data parallel tasks. It's a smoothly varying gradation. With a heterogeneous architecture, you'd have to choose between two (or even more) types of core, neither of which would be ideal, and with a substantial overhead for transitioning between the two.
Only after maximizing the data reuse.
No, after the serial task is done, process the parallel task with AVX and save having to transfer data and control to a different core.So, after a single core is done with it, just pass the pointer to the gpu.
And like I just said, there isn't really any transition between serial and parallel workloads. It can be tightly interwoven. Note that GCN will have a scalar ALU as well, to avoid the common case of repeating the exact same calculation for each work item. GCN will still choke on heavy scalar workloads though, but at least GPUs are taking the first baby steps toward a homogeneous architecture capable of handling any workload. CPUs merely have to implement AVX2 and to further scale performance/Watt there's AVX-1024.
The data is also in L2 cache, L1 cache, and even registers. You can benefit from data reuse at any level of the hierarchy.
Nick said:
And how many people are still running Celeron 300's overclocked to 450MHz?
In the fast moving world of personal computers technology is obsolete within 3-5 years and new devices are purchased by consumers that need them. Those that don't upgrade simply dont need/want new level of performance. They have other priorities.
Don't feed him. He conveniently forgets that generally programmable logic won't be able to cope any better in his example. Just because something could compute something doesn't mean it should.
Best trolling I have seen in years. I am done with this "discussion".
Not really... the problem is Nick just dismisses any evidence that runs counter to his way of thinking out of hand. FWIW, I think that Nick is right about much of what he says, just very wrong about when it is going to happen (he thinks it is a few years, I think it is a few decades...). You don't have to look very far back in this industry to find people making some outlandish claims about the way things will be 10 years in the future. Things rarely work out how people imagine...
There's no choice. Physics doesn't like homogeneous compute at this scale.
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iMacmatician
Regular
When do you guys think that Intel CPUs will have AVX-1024 (in 2008 Intel said it extends to 1024 bit FP and 512 bit integer—correct me if anything's changed since then)?
I'm going to assume Tick-Tock continues at ~1 microarchitecture / 2 years, and that AVX width changes only happen with microarchitecture changes (is this a safe assumption?).
If either INT or FP gets doubled per microarchitecture change, that gives:
2011 — Sandy Bridge — 128 bit INT / 256 bit FP
2013 — Haswell — 256 bit INT / 256 bit FP (this says Haswell's been delayed to 2014. Anyone know anything about that?)
2015 — SkyLake — 256 bit INT / 512 bit FP
2017 — SkyLake + 1 — 512 bit INT / 512 bit FP
2019 — SkyLake + 2 — 512 bit INT / 1024 bit FP
If both INT and FP get doubled per microarchitecture change (when possible), that gives 2017 — SkyLake + 1 — 512 bit INT / 1024 bit FP. Something quicker could give 2015 — SkyLake — 512 bit INT / 1024 bit FP.
Using the first sequence of values, if the number of cores doubles every 4 years and clock speed stays relatively unchanged, then (disregarding other changes) that means the INT/FP doubles every 2 years.
