Which devs would that be? Honest question.
It's from the Edge article they never said which dev it was.
Which devs would that be? Honest question.
It's from the Edge article they never said which dev it was.
of course it will be an issue...larger dev houses just have more resources to throw at obfuscated memory design than indies
As most dev/publishers are currently under NDA's with MS and PS4, most figured the devs in the Edge article would have most likely been Indies which would have a higher likelihood of having no prior experience with ESRAM or EDRAM from the 360. If you drop PC experience into the PS4 and X1, then you will get most immediate and higher rate of initial return on the PS4. Throw in that MS might be behind on their drivers (which has been alluded to via numerous sources), and the timing of when the Edge interviews took place, and there probably wasn't much API level support for utilizing the ESRAM as well.
I'm not so sure ESRAM will be an issue with teams at UBI, EA, etc..
I'm more interested in questions of bus contention, as data has to be moved. Everyone keeps adding bandwidth numbers without any consideration for the reads and writes to and from DDR3.
Compute is already a difficult problem for developers, but with esram, they also have to consider what compute is worth writing to the embedded RAM. What algorithms benefit latency, or bandwidth-wise, yet still need enough operations (3+?) to make esram beneficial?
I don't think this is the same situation as the Xbox 360 EDRAM.
I think the ESRAM is needed more this time around & devs are gonna have to try to get the most out of it to make up for the DDR3 68GB/s bandwidth.
Finding the best ways to use the ESRAM might be a pain right now for devs who hasn't figured out what work best when off loaded to ESRAM.
I'm more interested in questions of bus contention, as data has to be moved. Everyone keeps adding bandwidth numbers without any consideration for the reads and writes to and from DDR3.
Compute is already a difficult problem for developers, but with esram, they also have to consider what compute is worth writing to the embedded RAM. What algorithms benefit latency, or bandwidth-wise, yet still need enough operations (3+?) to make esram beneficial?
If the data is in the DDR, which most of it will be, and the operation is very bandwidth sensitive, it will have to be copied to eSRAM. Is there some magic where data in DDR can be processed with 100GB/s read and write bandwidth? And when that data is complete and needs to be replaced, it might be copied back to DDR? I don't quite understand the data flow for XB1, the 360 was simpler since it had less degrees of freedom.
If your algorithm needs to make copy, then you'll need to make copy in a DRAM-only design regardless, but on the X1 there's the Move Engine that saves you GPU cycles.
You can even have a frame that extends across both memory, logically they are one.
Given the capacity of the eSRAM, if whatever you're copying needs high bandwidth, it's getting read more than once.I think hes talking about how you have to use DDR3 bandwidth to move stuff from the DDR3 to the eSRAM, theres no way of getting around this, even if you the algorithm doesn't need to copy the data but it needs high bandwidth it needs to be copied into the eSRAM from the DDR3.
I think hes talking about how you have to use DDR3 bandwidth to move stuff from the DDR3 to the eSRAM, theres no way of getting around this, even if you the algorithm doesn't need to copy the data but it needs high bandwidth it needs to be copied into the eSRAM from the DDR3.
The Move Engines save you GPU cycles, but I don't really think many GPU's these days copy there own memory and waste cycles doing it that way .
I think hes talking about how you have to use DDR3 bandwidth to move stuff from the DDR3 to the eSRAM, theres no way of getting around this, even if you the algorithm doesn't need to copy the data but it needs high bandwidth it needs to be copied into the eSRAM from the DDR3.
The Move Engines save you GPU cycles, but I don't really think many GPU's these days copy there own memory and waste cycles doing it that way .
As if you read data from DRAM and "move stuff" back to the DRAM, you won't consume DRAM bandwidth?
You will but whats the point of that? other then making a copy.
Exactly.
and how do you propose to feed the DRAM at that rate to begin with?