So it wouldn't be possible for the cpu to supply lanes to 2 pci-e graphics slots and another controller to provide lanes to for example to 2 4 lane slots and a 1 lane slot ???
Well, in a word, "no", because how would that other controller connect to the system?
...Through PCIe, in today's PCs, which would eat some lanes coming off of your CPU.
and if not, is that just a limitation of cpu's that have onboard pci-e controllers
would cpu's that have no pci-e controllers and supply no pci-e lanes be immune from this ?
Not really a limitation, per se. In the past, as you may remember, x86 CPUs had no peripheral I/O at all (and before the Athlon 64 they didn't even have integrated memory controller I/O), they connected through a bus or a port to the chipset where all the I/O was located. So you could pile on a lot of I/O there, theoretically, but to actually get any use out of it, all of that data had to travel back and forth through that one link to the CPU, which created a bottleneck and added latency to the system.
Today's integrated PCIe is actually superior to the way things used to be, not only do we have faster I/O right on the CPU than the old connection to the chipset in previous generations of PCs, we actually have a connection to the chipset still, adding even more I/O power!
Back in the Core2 generation and before, a lot of peripheral I/O was still old PCI, which as you may remember was a shared, parallel bus. One device doing I/O blocked all other devices on that bus, and theoretical performance was hard-capped below original version 1 of PCIe 1x... So today's point-to-point PCIe is a decided upgrade, from just about every standpoint.