Will 256-bit Rambus XDR interface be viable this autumn?

[Dave B(TotalVR)]

Rambus is a serial memory interface right?


So I have a board with up to 4 chips on it. With the board running one chip, I have one XDR path to the 4 RAM chips, which are connected one after the other right? (like the RIMMS on old p4 mobos)

So when I add chip 2, is the XDR bus configurable enough to see the second chip is in, so give me a path to the second 2 memory chips. So now, with 2 chips I have chip 1 connected to ram 1+2 and chip 2 to ram 3+4.

When I put all 4 chips in, is it possible for the XDR interface to be configured again so that each chip has its own XDR path to its own RAM chip.


Now if you give each GPU chip 3 more XDR lines, so the chips also communicate with each other (and can hence get data across the right bus and other stuff)....

Surely thats a great way to produce a family of graphics boards with easily configurable rendering power brackets.

Surely that, in itself, is a great reson to jump on the XDR bandwagon as far as 3D graphics is concerned.

no?

 

[Xmas]

Rambus is a serial memory interface right?


So I have a board with up to 4 chips on it. With the board running one chip, I have one XDR path to the 4 RAM chips, which are connected one after the other right? (like the RIMMS on old p4 mobos)

No, this is not how XDR works. XDR is basically point-to-point, if you have a 64-bit XDR interface, you put e.g. four x16 chips in parallel, with 16 differential data lanes going to each chip.

 

[Dave B(TotalVR)]

So my 4 chip chip board using the same memory chips no matter how many are in will not work?

 

[_xxx_]

for a console 25.2GB/s ought to be enough to everybody?

I think so. The requirements will not be nearly as high as for the current high-end PC thanks to 100% optimized coding, so that should be a lot of bw there.

 

[_xxx_]

So my 4 chip chip board using the same memory chips no matter how many are in will not work?

I don't know about this specific case, but usually there is a "ready" line coming from each chip, or some kind of protocol going over the bus where the RAM chip does a "check-in", so the controller can automatically "recognize" the right mem config and reconfigure the settings/connections accordingly. Just like your PC-BIOS does "know" when you plug in another RAM chip.