The Amiga CD32 had an FPGA.
Chunky-To-Planar - The new magic hardware
The new Amiga CD32 contains a rather special new piece of hardware called a chunky-to-planar gate array. If you program games you'll instantly go 'wow!', but if you don't here's how it works, and why it's so good:
My mistake.I think that it was a VLSI gate array ASIC, it also replaced some of the functions of the Gary/Gayle chip chucking out things such as IDE support, etc.
FPGA's are economical for low volume devices only.
Why when they only cost a few dollars/cents in bulk anyway? FPGAs and ASIC are far more powerful than conventional CPUs at doing a limited range of tasks. A stratix 3 at 400MHz is 70-80 Gflops double percision of floating point performance and thats on chips from 2005. The "RPU" is powered by an Xilink II Vertex 6000 that runs at 66MHz but can draw 187 million raytraces at 15fps at a resolution of 640x480.
Just wondering why none of the main console makers ever use the fpga to accelerate a limited range of tasks like say drawing polygons or and/if's for AI.
I haven't priced FPGAs about 8 years, but at a previous job we used one (Xilinx Vertex II) for a video board. ASICs at the time were easily running double the clock rate for far less money. Since the market price for our board was at least few thousand dollars and low volume an expensive FPGA made sense.Why when they only cost a few dollars/cents in bulk anyway? FPGAs and ASIC are far more powerful than conventional CPUs at doing a limited range of tasks. A stratix 3 at 400MHz is 70-80 Gflops double percision of floating point performance and thats on chips from 2005. The "RPU" is powered by an Xilink II Vertex 6000 that runs at 66MHz but can draw 187 million raytraces at 15fps at a resolution of 640x480.
Just wondering why none of the main console makers ever use the fpga to accelerate a limited range of tasks like say drawing polygons or and/if's for AI.
Why when they only cost a few dollars/cents in bulk anyway? FPGAs and ASIC are far more powerful than conventional CPUs at doing a limited range of tasks. A stratix 3 at 400MHz is 70-80 Gflops double percision of floating point performance and thats on chips from 2005. The "RPU" is powered by an Xilink II Vertex 6000 that runs at 66MHz but can draw 187 million raytraces at 15fps at a resolution of 640x480.
Just wondering why none of the main console makers ever use the fpga to accelerate a limited range of tasks like say drawing polygons or and/if's for AI.
That's common enough. It's a lot faster than using software emulation!Actually, I remember that Ati/Nvidia used to use FPGA's for validation and testing before they made the actual chips.
I would think, but I'm no expert, that you would usually be able to clock your design a lot faster, perhaps >10x, in an ASIC.Not to mention that the same design implemented in ASIC is typically 10x smaller and clocks about 2x higher.
That's common enough. It's a lot faster than using software emulation!
I would think, but I'm no expert, that you would usually be able to clock your design a lot faster, perhaps >10x, in an ASIC.
How many FPGAs did you need to emulate the ASIC? I'd imagine that if you needed dozens of them to handle the design, then routing on and off multiple FPGAs is going to limit your clock speed <shrug>. Again, I haven't had to work with FPGA systems for many years so take my comments with the usual helping of salt.I am not an expert either. But the slowest FPGA system I have worked with was 25MHz. So a 10x speed-up seems questionable, especially with fully automated P&R and related stuff.
How many FPGAs did you need to emulate the ASIC? I'd imagine that if you needed dozens of them to handle the design, then routing on and off multiple FPGAs is going to limit your clock speed <shrug>. Again, I haven't had to work with FPGA systems for many years so take my comments with the usual helping of salt.
How many FPGAs did you need to emulate the ASIC? I'd imagine that if you needed dozens of them to handle the design, then routing on and off multiple FPGAs is going to limit your clock speed <shrug>. Again, I haven't had to work with FPGA systems for many years so take my comments with the usual helping of salt.