Waiting for the ISSCC...

[nAo]

..and unconvering new patents

There is a group of 3 new patents regarding CELL and various DMA mechanisms:

Cacheable DMA
Non-fenced list DMA command mechanism
DMA completion mechanism

..and this one, with a self-explanatory title:

Method and apparatus for managing the power consumption of a data processing system

I believe this is the first time we see how a CELL processor can manage DMA lists too (not just atomic DMA operations).
A DMA engine can process a plurality of outstading DMA operations and a DMA commands list can be tagged as fenced or not fenced. In the first case the DMA engine stops until all the DMA operations in the fenced list are completed and then it starts to work on the next DMA list. If a DMA list is tagged as not fenced then the DMA engine can work on different lists at the same time.
Obviously the first thing I'm thinking about is 'DMA lists = display lists'.
That stuff is neat but is not that different from how the PS2 DMA engine acts.. even if the PS2 DMA engine is not capable of processing more than one atomic DMA operation at the same time (on a single DMA channel!)
The patent about cacheable-dma requests is nothing new, since is almost a subset of the patent about DMA prefetch we already know..

ciao,
Marco

 

[Panajev2001a]

That is a definitive step-up from the PlayStation 2 DMA Controller as it is definately more flexible (the fenced mode is the modality of operation most similar to how the PlayStation 2 DMAC works) as well as being available to the SPU's/APU's while on PlayStation 2 everything had to be started/processed by the RISC core all the time (VU's were always spoon-fed by the RISC core in the EE).