I have heard that PS5 has no hardware VRS (no API, no microcode reference) as described above directly from two different graphics programmers working on PS5 games - two completely different dev studios. So I honestly am not sure why others say it does. I honestly trust the people I am talking to considering they are extremely competent.
That does not make the machine suddenly terrible or something. Maybe they can add in that to the SDK later on if it actually does support it in hardware - make an API portion of it just like MS has done. If not, well then it is just a difference between the machine's GPU capabilities.
Very interesting...
Does the PS5 have primitive shaders (as per AMD patent
https://patentimages.storage.googleapis.com/66/54/00/c86d30f0c1c61e/US20200193703A1.pdf) ?
Or instead mesh shaders (as described in MS patent for Index buffer compression:
https://patentimages.storage.googleapis.com/54/e8/07/67037358a9952f/US20180232912A1.pdf) ?
This MS patent in fact provides the most concise description (that I have found thus far) of what the mesh shader stage of the 3D pipeline actually is:
"In some implementations, referring to FIGS. 2B and 2C, each index buffer block
107 may be read by a mesh shader stage
91.
For example, mesh shader stage 91 may be a combination of any one or more of vertex shader stage 82, domain shader stage 88, and/or geometry shader stage 90. As such, the implementation according to FIG. 2B may have an understanding of compressed indices in the input assembler
80. Accordingly, logical pipeline
14b may not read and write indices. Further, in some implementations, when tessellation is enabled (e.g., in FIG. 2C), block index decompression may be performed in the input assembler and/or vertex shader stages. Additionally, when tessellation is enabled, the vertex shader stage may get merged with the hull shader stage, rather than with the geometry shader stage. When tessellation is disabled (e.g., in FIG. 2B), then the block index decompression may occur in the mesh shader stage.
During a vertex phase, mesh shader stage
91 may read the vertex position of a compressed index based on the original index reconstructed by the IA. Further, mesh shader stage
91 may transform the vertex position according to a transform function. Mesh shader stage
91 may store position in groupshared memory
109 along with the original index.
Mesh shader stage
91 may, during the primitive phase, read the connectivity information prepared by the input assembler
80. Mesh shader stage
91 may further read the transformed vertices out of groupshared memory
109. Additionally, mesh shader stage
91 may perform culling and if a primitive survives, then mesh shader stage
91 may indicate it as visible for the subsequent hardware. Further, each surviving vertex may be marked or indicated as such in groupshared memory
109.
During the attribute phase, mesh shader stage
91 may, for all surviving vertices output the vertex position, read the attributes from the vertex buffer
102, transform the attributes according to a transform function, and output the surviving transformed attributes. Subsequently, logical pipeline
14b may proceed to the rasterizer stage
94."