2006/2007 seems like the right time for R6XX. Don't you think?
http://www.physorg.com/news3965.html
Taiwan Semiconductor Manufacturing Company, unveiled its newest semiconductor manufacturing process today at a Technology Symposium attended by over 400 of the industry’s leading IC companies. First wafers are expected in December 2005.
The new 65nm Nexsys Technology for SoC Design allows designers to build logic devices with double the density of the company’s industry leading 90nm technology. This massive integration – the equivalent of more than 750 billion transistors on a single 12-inch wafer – enables significant cost savings to market movers across the IC industry.
Benefits of TSMC’s new process technology include a standard cell gate density twice that of TSMC’s 90nm Nexsys process; a 6T SRAM cell size of less than 0.5um2 (half that of its 90nm counterpart); and a 1T memory cell size that is a 65 percent smaller than the 90nm memory cell.
he 65nm Nexsys technology features an aggressive gate oxide thickness to further enhance transistor performance.
From a power and performance perspective, the 65nm Nexsys technology leads the industry with a 50 percent speed gain (TSMC’s 65nm General Purpose process versus its 90nm General Purpose process); and a 20 percent standby power reduction. High-speed 65nm versions are expected to lead the industry in power/performance tradeoffs.
In response to customer demand, TSMC’s first 65nm Nexsys technology, which will enter first production in December 2005, is optimized for low power. A high-speed version will be available in 2006, followed later in the year by a general-purpose 65nm process. A version employing SOI technology and an ultra-high-speed version will be introduced in 2007. Logic and mixed-signal options are slated for all versions, with embedded memory available in each.
http://www.physorg.com/news3965.html
Taiwan Semiconductor Manufacturing Company, unveiled its newest semiconductor manufacturing process today at a Technology Symposium attended by over 400 of the industry’s leading IC companies. First wafers are expected in December 2005.
The new 65nm Nexsys Technology for SoC Design allows designers to build logic devices with double the density of the company’s industry leading 90nm technology. This massive integration – the equivalent of more than 750 billion transistors on a single 12-inch wafer – enables significant cost savings to market movers across the IC industry.
Benefits of TSMC’s new process technology include a standard cell gate density twice that of TSMC’s 90nm Nexsys process; a 6T SRAM cell size of less than 0.5um2 (half that of its 90nm counterpart); and a 1T memory cell size that is a 65 percent smaller than the 90nm memory cell.
he 65nm Nexsys technology features an aggressive gate oxide thickness to further enhance transistor performance.
From a power and performance perspective, the 65nm Nexsys technology leads the industry with a 50 percent speed gain (TSMC’s 65nm General Purpose process versus its 90nm General Purpose process); and a 20 percent standby power reduction. High-speed 65nm versions are expected to lead the industry in power/performance tradeoffs.
In response to customer demand, TSMC’s first 65nm Nexsys technology, which will enter first production in December 2005, is optimized for low power. A high-speed version will be available in 2006, followed later in the year by a general-purpose 65nm process. A version employing SOI technology and an ultra-high-speed version will be introduced in 2007. Logic and mixed-signal options are slated for all versions, with embedded memory available in each.
