TSMC unveils new breakthroughs for Wafer on Wafer technology

[DavidGraham]

At the TSMC Technology Symposium, the largest contract manufacturer in the world introduced a new technology to connect chips. But instead of going through an interposer or more modern solutions like Intel's EMIB , two wafers are connected directly to each other.

The 3D stacking technology is called "Wafer on Wafer" (WoW for short) and stacks two wafers. Here are the first differences visible: Both wafers must be mirrored for this to work, which starts at the silicon level outside and continues beyond the front end of line (FeOL) and back end (BeOL).

The special feature is the lower wafer, which is pierced with TSVs ("thru silicon vias"). These under 10 microns fine strands should ultimately make contact with the second wafer. The TSV stacking technology has been well established, DRAM has been used for years and is now gaining ground in other areas. At TSMC, it will initially be used on System on Integrated Chips (SoIC). Further details will be revealed by the manufacturer but only in the future.

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[Bondrewd]

I've seen wafer stacking somewhere before.

A-anyway, it's another mobile-only stuff, the heat density kills it for everything else.

 

[Grall]

Yeah, it'd be like a miniature George Forman grill with two stacked dies facing each other.

 

[Tkumpathenurple]

Awesome news. I wonder how much of a paradigm change this will result in as we get closer to 3nm without a clear shrink afterwards in sight.

 

[Anarchist4000]

Yeah, it'd be like a miniature George Forman grill with two stacked dies facing each other.

Keep in mind the whole power profile changes when you start doing this. Once die area ceases to be a limiting factor you operate near threshold voltages all the time. The heat generated by a single die will fall significantly in the process. If designing with a 3rd dimension in mind you can also achieve far shorter wire lengths which can make a difference.

 

[Alexko]

Keep in mind the whole power profile changes when you start doing this. Once die area ceases to be a limiting factor you operate near threshold voltages all the time. The heat generated by a single die will fall significantly in the process. If designing with a 3rd dimension in mind you can also achieve far shorter wire lengths which can make a difference.

This assumes that you can afford to have each of the mm² of silicon you pay for bringing you less performance.

 

[eastmen]

This assumes that you can afford to have each of the mm² of silicon you pay for bringing you less performance.

can't you put something low power / heat under the hotter components. LIke put some edram / sram under the logic