Maybe a stupid question but what's a half node (also referred to as an optical shrink)?
It's a technology process that retains enough (almost all) characteristics of its parent node, so that you can use the same libraries, wire load models, etc., but that is smaller in size than the parent node. Since most of the characteristics are the same, a fab can roll out half-nodes much quicker than full nodes.
Basically, you design, synthesize and do the place and route of the chip as if you're designing for the parent node, deliver the layout to the fab, which then optically reduces the layout to the smaller half node. Half nodes are usually slightly faster, since signal travelling distances are a bit shorter, but electrically, the transistors are usually hardly if any faster than the parent node.
It's usually not possible to take an original, working, major node design and shrink it to its half node: analog cells often behave differently and certain digital characteristics may change enough to make them non-functional (slightly faster operation may result in hold time violations.) For analog cells, a common practice is to take the full node design, increase its size with the same amount it will be shrunk later on. The end result is an analog cell that's as big in the half node as it is in the full node and that behaves pretty much identical.
Since obviously process technology alone won't magically transform a design into something you can sell into handhelds.