The LAST R600 Rumours & Speculation Thread

It would be extremely surprising given that TSMC (where ATI is going to have this chip fabbed) has given no indication that it is yet capable of reliably manufacturing something as complex as R600 at 65nm with reasonable yields.

The consensus is that it's still a bit too early for a highly complex GPU at 65nm.

 

Yes, but the area of fins is only a fraction of what it could be, and that's what I'm wondering. Length of those fins is small and icreasing it should increase air flow, right?

 

Has ATI said that they intend to have R600 fabbed at TSMC? I've been assuming AMD themselves would make the high end while TSMC would make the low/mid range parts. If AMD is going to integrate SPs(GPUs) onto their chips they'd have to start somewhere. And it's safe to assume they intend on using 65nm to produce their CPUs in the future. I'd imagine the SP, unless a separate die, would be manufactured on the same process.

How much of a difference would there be between making GPUs and CPUs on a 65nm process?

 

Yes, They weren't planning on giving up on TSMC and UMC for production, partly because TSMC would allready be involved in the pre-production process. I can't imagine that AMD would like to start production with the most advanced GPU to date (advanced=hard to manufacture)

GPU's are far more advanced than CPU's given the same production process.

 

Yes, they are sticking with TSMC, as they designed for the TSMC process. AMD does not have spare capacities in their fabs, (too busy making CPUs) and is not set up for ATI designed chips.

If you think of how the initial suggestion of the 512bit external interface was received, R600 arriving on 65nm (at a time when AMD have only just started making their own CPUs on 65nm) would get about a hundred times more scepticism.

 

Great post.

Inspired, I looked-up the picture of G80:

http://www.beyond3d.com/images/news/g80core.jpg

and had a quick count of what I guess are the pads.

~5700

Whilst the package has something like 1600 balls, if I remember correctly. The vast majority of the pads are involved in power, I think the picture makes that pretty clear.

So, the fundamental problem appears to be fitting balls onto the package, not pads on the die's surface.

In which case, I think that quenches any remaining angst about R600 being refreshed in 65nm form, and being unable to support a 512-bit bus. The die size, per se, is not what's limiting the bus size. This seems to be where this patent application comes in, solving the packaging problem:

Method for reduced Input Output Area

while there's no problem with pads.

Thanks for clarifying this stuff

Jawed

 

But how much of that capacity would be used up by manufacturing only R600? And from a financial standpoint what's more profitable, 65nm CPUs or unstoppable GPUs which would increase the sales of CPUs? Utterly dominating the GPU field could give them a significant marketing boost and how beneficial would pure 65nm CPUs be at competing with Intel right now. 65nm CPUs would help but would it be that much of a difference without an improved architecture and how many would they need?

I know the idea is out there a bit but there appears to be some logic to it. Plus how much more production is AMD needing for CPUs right now, especially if it looks like they're having trouble against the Core chips?

 

1. There is more money and volume in CPUs.
2. The AMD fabs are not set up for the ATI designs. By the time that happens, R600 will be superceded.

You can't just take a design from one fab and drop it into another one at a few months notice. While your ideas of market advantage may be true, it's something that AMD is planning on doing for the future as the two company's product roadmaps merge. It's most likely things will start to happen for R700/R800 or Fusion products. It's simply not something that is viable for a GPU that must be moving into volume production any day now, least of all at 65nm that AMD has only just got working for it's CPUs.

This has already been covered in the threads on the ATI/AMD merger and the Fusion product. All the information (both speculation and official statements) are in there if you want to use the search function.

In summary, R600 is very, very unlikely to be 65nm or fabbed at AMD. You won't find anyone with any standing on these forums that support that view, or any statements from ATI or AMD to that effect. In fact they've stated they'll continue to use TSMC and other partners for fabbing for quite some time.

 

- AMD has no experience in GPU production, even less for huge parts
- AMD uses SOI process (no GPU has ever been done on SOI yet)
- a chip is designed for a specific process and that takes time, the merger isn't event 2 months old
- AMD is capacity constrained
- CPU have pretty margins compared to GPU

I can't see why or how AMD would go this way in the coming months.

Going back on topic, do we know how much Xenos does consume ?

Edit : damned, to slow.

 

In general, you can have almost the same effect by having a large number of fins with a smaller area or a smaller number with a large area, but it's a matter of costs and size, and it's easier to cool uniformely smaller single fins.

 

I'm pretty much convinced that the ATI patent has nothing to do with GPUs: it has the smell of wire bonding all over. And that not only because it contains the term 'wire bond' 8 times.

The patent tries to come up with a way to reduce the amount of active area needed to connect power pads by connecting 2 pads to 1 active area. In wire bonding, you can have a 2 deep ring of bonding pads. The center of pad in the inside right must fall right inbetween the pads on the outside ring. The technical term is a 'staggered pad ring' and it's shown in figure 7. (In the past, this was solved by literally bonding 2 wires to 1 pad, but that's probably not allowed anymore with staggered IO's.)

For flip-chip that's a non-issue, as clearly shown on the G80 die shot: on the outside it has 4 pad rings that are decidedly not staggered!

This patent is something that would be relevant for an external VIVO, a south bridge, or a handheld chip, where pad-limited designs are always a problem.

 

Glad for the insight! Seems I went for the pix more than the text

I originally made the connection because of the staggered balls round the perimeter of the supposed R600:

​

which seems to increase the density of balls there, which I was guessing would be for the 512-bit bus.

Jawed

 

You do realize you're using the ball layout that was photoshopped by a couple of jokers having a good time, right? The original picture doesn't have the rotated inside rectangle.

But I don't know the reason for the different densities. That's for package_guy to answer.

It could be for thermal reasons also: the heat from the die flows via the heat sink to the outer aluminum ring. The PCB is also a big factor in removing excess heat. The substrate itself conducts less, so it'd make more sense to increase the ball density under the aluminum ring than at places where there's only substrate. Pure speculation though.

 

LOL, I just went through the old thread looking for a picture with staggered balls.

Jawed

 

1449 to be exact. http://www.beyond3d.com/forum/showthread.php?p=885238#post885238

 

Jawed might be counting a number of pads on the G80 die not the balls under its chip

Silent_guy, it's the great posts replying Jawed, but Jawed you are great too

Jawed's idea seems to fell short hand... Silent_guy, could you please elaborate any ideas or techniques now available those allows to connect such a huge number of balls and connections as on the susposed R600 on the 65nm die shink?

Edit: Typo...

 

Hey, that looks like my handiwork!


-Joker

 

Jawed just called, he wants three hours of his life back

 

Not necessarily.

I conveniently avoided giving my opinion about that to hide the fact I don't know.

There are a number of questions that need an answer.

1. What's the minimal pad pitch on the die?
2. What's the area of an active buffer?
3. How many power pads do you need per IO pad?
4. How many functional IO's are there in total on the die?
5. Can you put core logic under IO pads?

I think that one of the problems that could emerge is that the amount of area fully dedicated to IO alone will become too large. So the ratio IO/core will increase and the final die size won't scale optimally with the process. At that point, it becomes a discussion of economics.