The future of MGPU design
- Thread starter Freak'n Big Panda
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Freak'n Big Panda
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the GDDR5 protocol is really the only option for a fast enough interconnect unless a custom protocol was designed. The issue with it is that the GDDR5 IO controllers suck a lot of power. So a switch chip solution in which would require double the IO controllers would probably not be feasible once the power draw was factored into the equation.
Easy way to prove (or disprove) your point here: clock a 4850 and 4870 identically and measure the difference in power draw. I think you'd be proven quite wrong, at that point. IOW: power draw on I/O is insignificant compared to the power draw of other logical blocks.
Freak'n Big Panda
Regular
I know for a fact that power draw for the GDDR5 IO interface is very significant.
This one works and is really low overhead : "no one renders on my fucking turf, got that?"
Yes, of course. But I said that from the point of view of connection between the gpu's and the memory. What you are saying here is SFR.
SFR merely tells you how each frame is rendered, it's split between gpu's (may be 50-50, may be not). It does not mandate any particular connection between gpu's and memory. The discussion prior was regarding connection between gpu's and memory, though if you have any ideas on splitting the workload more efficiently b/w gpu's, I am all ears.:smile:
It's used with tiles inside the GPU, and that's how you would use it here.
Coherency inside GPUs is far from general. There IS a mandatory connection between SIMD-Engines and memory inside the HD3000 architecture for instance, and I doubt it's any different for others.
Coherency inside GPUs is far from general. There IS a mandatory connection between SIMD-Engines and memory inside the HD3000 architecture for instance, and I doubt it's any different for others.
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Well I wasn't very clear, I edited the post.
Generally what happens inside GPUs is close to what we called SuperTiling and that could work equally well with coupled GPUs if there were enough bandwidth to communicate transformed vertices (presently there isn't, also the GPUs aren't really designed to be able to scale in this manner).
Generally what happens inside GPUs is close to what we called SuperTiling and that could work equally well with coupled GPUs if there were enough bandwidth to communicate transformed vertices (presently there isn't, also the GPUs aren't really designed to be able to scale in this manner).
Well, with the rather limited information released by intel on larrabee, what do the more knowledgeable folks here think of it scalability (as in X2 cards). As for me, I think it is a slam dunk since the entire pipeline is now implemented in software and as multi-CPU boards are a much understood thing. Though the initial cards might not show/implement multi-larrabee scalability, IMHO, it's going to be much easier for intel to build multi-larrabee cards than for ATI/nvidia that actually scale linearly in most (if not all) of the games.
What do you think?
What do you think?
It's not clear to me that we would expect Larrabee to scale linearly, though its basic high-level infrastructure appears better suited to an X2 type card.
Not sure about the physical details though, such as how much connectivity the first chips will have and details about die size, board layout, and power consumption, which can lead to a delay in multichip boards.
Not sure about the physical details though, such as how much connectivity the first chips will have and details about die size, board layout, and power consumption, which can lead to a delay in multichip boards.
Yes. these sort of details are the ones that can sink any chances of X2 cards appearing. Power could be a real killer. I clearly remember fudo reporting ~300W powerdraw for larrabee.
Hopefully, they will be able to lower it with passage of time and we will actually see X2 boards.Expect them to cost an arm, a leg and an ear (if they appear).
