RWT: QPI 1.1

[AlNom]

Our friendly neighbourhood CPU guru, David Kanter at RealWorldTech, has a look at Intel's QPI in Sandy Bridge and thoughts for future development.

To adjust to changes in the industry and system architecture, Intel has announced a second generation Quick Path Interconnect 1.1. This new version is backwards compatible with existing QPI interfaces, which are now collectively referred to as QPI 1.0. All current x86 and IPF platforms use QPI 1.0 – including Nehalem-EP/EX, Westmere-EP/EX and Tukwila. QPI 1.1 further unifies the x86 and IPF flavors, so that Itanium can re-use and benefit more from the tremendous investments in x86 system architecture. The goal for the next generation QPI is higher performance, better efficiency and reliability. To that end, QPI 1.1 has numerous improvements at the electrical, logical and protocol levels. Sandy Bridge-EP and the Romley platform will be the first products to use QPI 1.1, followed by Ivy Bridge-EP/EX, and it is possible that Poulson will follow suit.


Be sure to read the entire article here.

 

[Davros]

There are enough PCI-E lanes to handle dual-GPU

so we will no longer need those sli connector thingy's ?

Since an IOH is no longer needed, there is no reason to include QPI in consumer parts – only PCI-E and Intel’s Direct Media Interface (DMI, for use with the Southbridge) are needed. Going forward, QPI is primarily for servers and workstations.

So either sandy isnt a consumer part or it doesnt include qpi ?

Changes in the industry such as the trend towards multi-core, greater integration and better NUMA support in mainstream operating systems

we need better Numa support

 

[I.S.T.]

He meant everything after Sandy Bridge.

 

[Grall]

so we will no longer need those sli connector thingy's ?

No, I'm sure the thingys will continue to haunt us for the foreseeable future; they allow a lower level, more direct connection between the GPUs, most assuredly lower latency too since there's no need for arbitration, and no bus contention with other devices either.

So either sandy isnt a consumer part or it doesnt include qpi ?

Socket 1100 hasn't ever had QPI to begin with, and I don't think it's about to gain it in the future either. With PCIe integrated on the CPU die itself, QPIs only need is for multiple CPU sockets, and socket 1100 doesn't support that.

 

[3dilettante]

I find it interesting that QPI has slowly floated out of reach of the consumer segment.
While at the outset, it had more market overlap with Hypertransport-based interconnects, it seems to have become even more upmarket.

The volumes of desktop parts are traded for the more fully shared platform with Itanium. At least in terms of units, it probably isn't a net gain. It's not a botique interconnect, though could some future higher-RAS PCIe start to nibble at the bottom of the workstation and low-end server market, perhaps if some of the talk of cache-coherent PCIe ever comes to fruition?

edit:
I concede that PCIe latency is not too good in comparison, but in some kind of cheap-o cloud server, is it all that bad?


I don't know where HT fits in this, though with its primary driver in QPI's altitudes is AMD's slipping presence in servers and HPC, it seems to be in a decline that may only be punctuated by Bulldozer.

 

[rpg.314]

I don't see why Intel or AMD will do anything but proprietary coherency-over-PCIe

 

[3dilettante]

AMD's FSA promises (someday, maybe) a unified and coherent memory space for CPU and discrete GPU, which presumably would be linked by PCIe.

AMD at least seems to give lip service to a non-proprietary solution.

 

[rpg.314]

AFAICS, FSA is a sw interface to underlying hw. Assuming intel buys into - or is arm twisted into buying into - the FSA premise, both AMD and Intel could do proprietary PCIe coherency extensions, implement FSA and still cut nv out of the picture.

IOW, implementing FSA does not require a standardized coherency-over-PCIe protocol.