R9500 Clarification..

[8ender]

I'm not sure if I read it here but doesn't ATI have the option of disabling part of the 9700 core if the part isn't fabbed to spec?

I read somewhere that these parts would essentially be the 9500 part.

If so does anyone know which parts? I know it was 2 of something (pipelines?) that ATI could disable.

If ATI has this ability, I predict that the 9500's are probably already rolling off the lines at TSMC. Likely though, ATI isn't going to release the 9500 until the 9700 excitement has died down.

 

[alexsok]

The only info about R9500 currently floating around the net is that it wil be 4x1... Thus, i assume it will loose to GF4TI4600 in most tests, although it will be a DX9 part and that's a big advantage!

I wonder how it will differ from R9700, besides the reduced pipelines...

 

[Simon Templar]

Hmm... Could this explain why the temp registers are 32 but only 16 are exposed in the drivers?

When they disable the 1/2 the pipes the chip would still have the correct number of temp registers to meet the DX9 specs....

-Simon

 

[alexsok]

Hmm... Could this explain why the temp registers are 32 but only 16 are exposed in the drivers?

When they disable the 1/2 the pipes the chip would still have the correct number of temp registers to meet the DX9 specs....

-Simon

Yeah, that sounds pretty reasonable...

 

[8ender]

yeah it was pre-planned by ATI when they built the chip so that they could salvage the cards that didn't cut it, thus making a lot more profit.

Its a really slick idea when you think about it.

I wonder what percentage of chips fabbed could be sold with this process?

I hope nVIDIA has something akin to this in store, those yields for NV30 sounded awful.

 

[Joe DeFuria]

There are two rumors about the 9500, one is that it will be 4x1 as Alexsok said, and the other is that it would be 128 bit memory bus. Essentially, this would make the 9500 pretty much exactly "1/2" of the 9700.

Thus, i assume it will loose to GF4TI4600 in most tests, although it will be a DX9 part and that's a big advantage!

Actually, (if we assume the 9500 is clocked similarly to the 9700), a 4x1 9500 would probably beat the 4600 in the important tests, IMO: with aniso and AA enabled. Where it would loose to the 4600 would likely be in high resolution tests without AA / aniso.

That being said, pricewise, the 9500 will probably compete more directly with the 4400, not the 4600.

More difficult to guess will be Doom3....I have no idea if a 9500 would beat a GeForce4ti there. For this case, a lot probably depends on shading / dot-3 performance, stencil performance, etc. Things that specs have a hard time predicting....

There are really too many unknowns about the 9500 to do any real meaningful speculation though...if we assume 4x1 with 128 bit bus, a lot will be depending on core clock and memory that ATI pairs it with...

 

[RussSchultz]

Probably (though I'm just theorizing here), the defects that exhibit themselves on the 9700 die won't be regular enough to harvest sufficient quantity for a 9500 part(assuming the half the pipes are what's in store). So, the only way to use the same die for both parts is by taking a margin hit on the cheaper part--which is the one you'd sell more of so that doesn't make much financial sense.

Given that they could shrink the die by removing some of the pipes (and hence, increase yield, reduce cost, increase margin, etc), that mode would make more sense, rather than trying to revive bad parts.

 

[Dave Baumann]

I'd just like to point something out that may indicate what chip is being used for 9600:

http://www.beyond3d.com/reviews/ati/radeon9700pro/index.php?page=page6.inc

(just under the close up of the board)

 

[Maverick]

Hmm... Could this explain why the temp registers are 32 but only 16 are exposed in the drivers?

When they disable the 1/2 the pipes the chip would still have the correct number of temp registers to meet the DX9 specs....

No, the number of temp registers is per pipe, otherwise each pipe would only have two temp registers each, which would be very restrictive...

 

[8ender]

Interesting thought, perhaps the disabling is simply there to make the 9500 a more convenient part to produce.

But wouldnt the disabling help out a little with yields?

 

[Dave Baumann]

No, the number of temp registers is per pipe, otherwise each pipe would only have two temp registers each, which would be very restrictive...

No, I think thats in total.

IIRC GF3 had 8 Pixel Shader registers in total, and this was configured as two per pipe - however if all 8 needed to be used then it would effectively pipeline combine.

 

[psurge]

That makes no sense. If 1 pixel pipe needs all 16 registers, the 7 other pipes idle while 1 pipe cranks away? And then if that 1 pipe needs to access a register it potentially has to read/write it 7 pipes away on the chip? That sounds... really dumb.

 

[Dave Baumann]

Well, put it like this, is there really enough die space for 256 register combiners....?

 

[Basic]

Not 256 register combiners, 256 registers. Big difference.
Just to be clear, I'm not talking about GF3. (And neither does psurge.)

 

[Maverick]

I think the number of transistors required for 256 registers is probably smaller than the number needed to arbitrate requests for 16 registers from 8 different pipes...

 

[Nagorak]

Probably (though I'm just theorizing here), the defects that exhibit themselves on the 9700 die won't be regular enough to harvest sufficient quantity for a 9500 part(assuming the half the pipes are what's in store). So, the only way to use the same die for both parts is by taking a margin hit on the cheaper part--which is the one you'd sell more of so that doesn't make much financial sense.

Given that they could shrink the die by removing some of the pipes (and hence, increase yield, reduce cost, increase margin, etc), that mode would make more sense, rather than trying to revive bad parts.

I honestly don't know much on this subject, but it seems to me that they could easily get quite a few parts this way if their yields are fairly good. If half the chips coming off the line are melted slag, then I guess it wouldn't work, but if most of them more or less work. Keep in mind, that if only a single pipe on the card doesn't work, it can't be a Radeon 9700, but if you just disable the other 3 it can be a Radeon 9500. For that matter, maybe if we're lucky they'll find out they only need to disable 2 pipes or something.

I mean, it works for Intel, right? I don't see why it couldn't work for ATi.

I guess if another part of the chip besides the pipes is jacked, they'll just have to toss it into the can. But it's my understanding that the pipes take up most of the transistor count (and die space) of the chip and thus percentage wise are more likely to be faulty.

Depending on yields though, and exactly what part of the chips usually fails, there does seem to be a chance we won't see many 9500s though. :-\

 

[Entropy]

As far as I know, the only reasonably firm information is from an article at DigiTimes, which stated that the R9500 would have a lower pin-count than the R9700. The conclusion that it would have a 128-bit memory interface is seductive, but it is not the only option that would fit. According to earlier estimates, the 9500 should be presented to the public just about now, so the answers shouldn't be too far away. Failing that, lets hope for a good leak.

Entropy

 

[Basic]

Ohh, and then we have the Radeon 9632.43 with 3 functional vertex pipelines and 5 functional pixel pipelines (or maybe 6 if you clock it slightly lower). This idea will bring the fine level product diferentiation to whole new level.


OK, a little more serious. What kind of errors can you get on the chips, and what's the size of them? From what I understand there's two kinds.

The first kind, that limit yield due to speed is usually "large" in physical size. If one chip can be clocked at X MHz, then all chips on that wafer will likely handle a similar speed.

The second kind, is particles that completely breaks the function of the surrounding gates, no matter what the frequency is.

At least that's how I understood it, but with the stuff we've done it's not interesting to test anything else than "works with the specifed margin", speed binning is uninteresting. So I don't have any experience with that.

Russ (or anyone else that's worked with it), would you agree with that description? And in that case, what part is usually the biggest problem? And how large are the "point-errors" counted in gates? I'm thinking about what granularity you need to add redundancy to make it work.

 

[Maverick]

Depending on yields though, and exactly what part of the chips usually fails, there does seem to be a chance we won't see many 9500s though. :-\

I don't think that's likely to be a problem. Even if they get a 100% 9700 yield, there's going to be an absolute limit on the number of 9700s that they can sell, so they can just turn off the extra pipes etc of the excess ones, and badge them as 9500, and there would be no way for the average Joe to know.

Of course, maybe there will be a registry hack to turn on the deactivated pipes. If you're lucky, you could end up getting an actual 9700!

 

[Neeyik]

Just thinking about this business of registers and pipelines, the DX SDK states that "...registers transfer data to the shader ALU and store temporary results...", which to my brain means that each ALU has its own set of registers (which would explain why the PS section of a DX8 chip core is so large). I was wondering about the Trident XP-thingamabob with the pipelines sharing resources; now it's supposed to have 4 pixel pipelines so that must surely mean 4 ALUs, yes? Is it possible that the "sharing of resources" refers to the registers?