R700 Inter-GPU Connection Discussion

Discussion in 'Architecture and Products' started by Arty, Jun 28, 2008.

  1. no-X

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    It's very simple. The middle chip is FBI (frame-buffer interface) and the outer chips are TMUs. There's also a SLI connector and two display connectors (one for 2D input and the second one for monitor). Just a simple copy of 3Dfx Voodoo 2. Evident lack of invention. Shame on ATi! The end is near... :shock:

    [​IMG]
     
  2. w0mbat

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    Because u can :wink:
     
  3. ShaidarHaran

    ShaidarHaran hardware monkey
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    In the first slide linked, I see mention of "shared memory". Is this referencing internal memory (caches/register files/fifo buffers/local stores/etc.) or would I be foolish to get my hopes up that this implies R700 may indeed have a shared memory pool?
     
  4. ShaidarHaran

    ShaidarHaran hardware monkey
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    Not necessarily. No need to spend money on R&D and production when you have a supplier that has already done so, and quite well and for some period of time, at that.
     
  5. no-X

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    just one detail:

    RV670 is 256bit and 190mm2
    RV770 is 256bit, but 260mm2

    Dave (or Eric?) said, that they were pad-limited at 8 SIMDs. So there is about 60mm2 of die for pads, which wasn't required on R670. Any idea, what good is it? I don't think GDDR5 are so "pads-hungry", so majority of them is likely used for X2 inter-die communication. How much pads fits in 60mm2? And how wide could that bus be?
     
  6. Jawed

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    GDDR5 seems to require 61 pins per 32-bit memory channel, on the GPU. Not sure what's required by GDDR3, can't find any info.

    Also the CrossFireX Sideport looks like it consumes a lot of pins, just because it appears to have a lot "units". Who knows.

    http://forum.beyond3d.com/showpost.php?p=1181681&postcount=56

    Jawed
     
  7. fellix

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    Not much, really:

    [​IMG]
     
  8. Sinistar

    Sinistar I LIVE
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    Can anyone tell how wide the pci-e ports are by that picture?
     
  9. fellix

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  10. Jawed

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    I haven't a clue why PCI Express is being discussed. The CrossFireX sideport, I reckon, is that blue section over on the right edge.

    Jawed
     
  11. Sinistar

    Sinistar I LIVE
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    I don't know, I just had this strange idea after seeing that picture.
    Why have two pci-e ports to begin with?
     
  12. fellix

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    Nope. ;)

    Probably, you all are familiar of how a row of planar serial transceivers should look like, and namely a full single 16-lane PCIe one. Here are few examples (clamped in red box):

    [​IMG]
    R520

    [​IMG]
    G200

    [​IMG]
    G80
     
    #32 fellix, Jun 29, 2008
    Last edited by a moderator: Jun 29, 2008
  13. Mark

    Mark aka Ratchet
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    If it's perfectly transparent to the user (and the games being played) then congrats, multi-GPU is finally viable. If people are messing around renaming .exe files or waiting for profiles for games to work right and all the BS, then no thanks.
     
  14. Jawed

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    I'm interpreting those "two PCI Express ports" as the GPU side of bifurcation support:

    http://www.elitebastards.com/pic.php?picid=hanners/ati/cat83/Slide14.jpg

    i.e. each port is 8 lanes wide and a pair of them together makes for a full 16 lane configuration in most PCs.

    Bifurcation then relies upon the northbridge.

    I can't see the pix you've posted Fellix :sad:

    Jawed
     
  15. Sinistar

    Sinistar I LIVE
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    Well my eye sight is bad, but it almost looks like 2 x 32 lane pci-e ports.

    Probably wrong though.
     
  16. fellix

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    Well, sort of.
    HyperTransport interfacing is very similar on view.

    Feeding my thoughts on that, how much have to drop the PCIe latency (x16 link), to facilitate a viable cache coherency updates (remote resource access)? I'm just thinking of how ATi could strip down and implement a custom framing low-latency protocol for that side-port link...
     
    #36 fellix, Jun 29, 2008
    Last edited by a moderator: Jun 29, 2008
  17. MfA

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    There's no need for cache coherency in rasterization.
     
  18. Sinistar

    Sinistar I LIVE
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    could that explain the large number of ports on the PCI-E chip?
     
  19. fellix

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    That's right - I just added it as an example to the inter-chip latency issue. ;)
     
    #39 fellix, Jun 29, 2008
    Last edited by a moderator: Jun 30, 2008
  20. rwolf

    rwolf Rock Star
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    Perhaps with an interconnect they can treat two GPUs as one from a driver perspective.
     
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