I recently saw the recent pictures of the chip layout of the EDRAM and was wondering why it looks to be seperated into 4 sections (see pics posted by Dave in the chip source reference question)? Is this to help with parallelism or is it a breakdown in the terms of the logic that it contains?
Sorry if this has been asked before but I couldnt find under the search function other then the EDRAM general info. Any breakdown of the chip would be appreciated now that we have pics
Sorry if this has been asked before but I couldnt find under the search function other then the EDRAM general info. Any breakdown of the chip would be appreciated now that we have pics